mpm/fpga: x4xx: Major updates in preparation for future devices

FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223

top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf

@@ -827,14 +827,14 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_TX_LED
 set_global_assignment -name VERILOG_FILE ../zbx_top_cpld.v
 set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_decoder.v
 set_global_assignment -name SDC_FILE ../../../../constraints/timing/shared_constants.sdc
-set_global_assignment -name SDC_FILE ../../../../cpld/db_spi_shared_constants.sdc
+set_global_assignment -name SDC_FILE ../../../../cpld/x410/db_spi_shared_constants.sdc
 set_global_assignment -name SDC_FILE ../zbx_top_cpld.sdc
 set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer_impl.v
 set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer.v
 set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/reset_sync.v
 set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_splitter.v
-set_global_assignment -name VERILOG_FILE ../../../../cpld/spi_slave.v
-set_global_assignment -name VERILOG_FILE ../../../../cpld/spi_slave_to_ctrlport_master.v
+set_global_assignment -name VERILOG_FILE ../../../../cpld/common/spi_slave.v
+set_global_assignment -name VERILOG_FILE ../../../../cpld/common/spi_slave_to_ctrlport_master.v
 set_global_assignment -name VERILOG_FILE ../register_endpoints/basic_regs.v
 set_global_assignment -name VERILOG_FILE ../register_endpoints/power_regs.v
 set_global_assignment -name VERILOG_FILE ../register_endpoints/switch_control.v
@@ -847,7 +847,7 @@ set_global_assignment -name VERILOG_FILE ../register_endpoints/lo_control.v
 set_global_assignment -name VERILOG_FILE ../zbx_cpld_core.v
 set_global_assignment -name VERILOG_FILE ../../../ctrlport_byte_deserializer.v
 set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v
-set_global_assignment -name VERILOG_FILE ../../../../cpld/reconfig_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../cpld/common/reconfig_engine.v
 set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_combiner.v
 set_global_assignment -name VERILOG_FILE ../register_endpoints/atr_controller.v
 set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../../lib/control/ram_2port_impl.vh