mpm/fpga: x4xx: Major updates in preparation for future devices
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
This commit is contained in:
Javier Valenzuela
committed by
Martin Braun
Martin Braun
co-authored by
Wade Fife
Ryan Marlow
Martin Braun
Humberto Jimenez
Wade Fife
Ryan Marlow
Martin Braun
Humberto Jimenez
parent
ffdcc016cc
commit
adf6f576c6
+46
-156
@@ -30,11 +30,6 @@ module cpld_interface (
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// Reset (domain: pll_ref_clk)
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input wire ctrlport_rst,
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// Timestamp (domain: radio_clk)
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input wire [63:0] radio_time,
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input wire radio_time_stb,
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input wire [ 3:0] time_ignore_bits,
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// AXI4-Lite: Write address port (domain: s_axi_aclk)
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input wire [16:0] s_axi_awaddr,
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input wire s_axi_awvalid,
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@@ -64,8 +59,6 @@ module cpld_interface (
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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@@ -91,7 +84,8 @@ module cpld_interface (
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`include "../../lib/rfnoc/core/ctrlport.vh"
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`include "regmap/pl_cpld_regmap_utils.vh"
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`include "cpld/regmap/mb_cpld_pl_regmap_utils.vh"
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// Variant-dependent register map.
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`include "cpld/regmap/x410/mb_cpld_pl_regmap_utils.vh"
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`include "cpld/regmap/pl_cpld_base_regmap_utils.vh"
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//---------------------------------------------------------------------------
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@@ -103,28 +97,6 @@ module cpld_interface (
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assign s_axi_areset = ~s_axi_aresetn;
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assign ctrlport_clk = pll_ref_clk;
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//---------------------------------------------------------------------------
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// Timestamp synchronization
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//---------------------------------------------------------------------------
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reg [ 3:0] radio_time_stb_shift_reg;
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wire radio_time_stb_prc;
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reg [63:0] radio_time_prc;
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// radio_clk and pll_ref_clk are synchronous clocks with an integer
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// multiplier <= 4.
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//
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// A simple register can be used to capture the latest timestamp the strobe
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// pulse is preserved for up to 4 clock cycles and used in pll_ref_clk domain
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// to driver timers.
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always @(posedge radio_clk) begin
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radio_time_stb_shift_reg <= {radio_time_stb_shift_reg[2:0], radio_time_stb};
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if (radio_time_stb) begin
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radio_time_prc <= radio_time;
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end
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end
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assign radio_time_stb_prc = | radio_time_stb_shift_reg;
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//---------------------------------------------------------------------------
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// MPM Endpoint connection
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//---------------------------------------------------------------------------
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@@ -134,12 +106,10 @@ module cpld_interface (
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wire [19:0] mpm_endpoint_ctrlport_axi_clk_req_addr;
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wire [ 3:0] mpm_endpoint_ctrlport_axi_clk_req_byte_en;
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wire [31:0] mpm_endpoint_ctrlport_axi_clk_req_data;
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wire mpm_endpoint_ctrlport_axi_clk_req_has_time;
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wire [ 9:0] mpm_endpoint_ctrlport_axi_clk_req_portid;
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wire mpm_endpoint_ctrlport_axi_clk_req_rd;
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wire [15:0] mpm_endpoint_ctrlport_axi_clk_req_rem_epid;
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wire [ 9:0] mpm_endpoint_ctrlport_axi_clk_req_rem_portid;
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wire [63:0] mpm_endpoint_ctrlport_axi_clk_req_time;
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wire mpm_endpoint_ctrlport_axi_clk_req_wr;
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wire mpm_endpoint_ctrlport_axi_clk_resp_ack;
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wire [31:0] mpm_endpoint_ctrlport_axi_clk_resp_data;
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@@ -177,8 +147,8 @@ module cpld_interface (
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.m_ctrlport_req_rem_portid (mpm_endpoint_ctrlport_axi_clk_req_rem_portid),
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.m_ctrlport_req_data (mpm_endpoint_ctrlport_axi_clk_req_data),
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.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_axi_clk_req_byte_en),
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.m_ctrlport_req_has_time (mpm_endpoint_ctrlport_axi_clk_req_has_time),
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.m_ctrlport_req_time (mpm_endpoint_ctrlport_axi_clk_req_time),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_axi_clk_resp_ack),
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.m_ctrlport_resp_status (mpm_endpoint_ctrlport_axi_clk_resp_status),
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.m_ctrlport_resp_data (mpm_endpoint_ctrlport_axi_clk_resp_data)
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@@ -186,16 +156,14 @@ module cpld_interface (
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// Transfer AXI clock based MPM endpoint control port request to pll_ref_clk
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// domain.
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wire [19:0] mpm_endpoint_ctrlport_pll_clk_req_addr;
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wire [ 3:0] mpm_endpoint_ctrlport_pll_clk_req_byte_en;
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wire [31:0] mpm_endpoint_ctrlport_pll_clk_req_data;
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wire mpm_endpoint_ctrlport_pll_clk_req_has_time;
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wire mpm_endpoint_ctrlport_pll_clk_req_rd;
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wire [63:0] mpm_endpoint_ctrlport_pll_clk_req_time;
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wire mpm_endpoint_ctrlport_pll_clk_req_wr;
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wire mpm_endpoint_ctrlport_pll_clk_resp_ack;
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wire [31:0] mpm_endpoint_ctrlport_pll_clk_resp_data;
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wire [ 1:0] mpm_endpoint_ctrlport_pll_clk_resp_status;
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wire [19:0] mpm_endpoint_ctrlport_req_addr;
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wire [ 3:0] mpm_endpoint_ctrlport_req_byte_en;
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wire [31:0] mpm_endpoint_ctrlport_req_data;
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wire mpm_endpoint_ctrlport_req_rd;
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wire mpm_endpoint_ctrlport_req_wr;
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wire mpm_endpoint_ctrlport_resp_ack;
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wire [31:0] mpm_endpoint_ctrlport_resp_data;
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wire [ 1:0] mpm_endpoint_ctrlport_resp_status;
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ctrlport_clk_cross ctrlport_clk_cross_mpm (
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.rst (s_axi_areset),
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@@ -208,63 +176,25 @@ module cpld_interface (
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.s_ctrlport_req_rem_portid (mpm_endpoint_ctrlport_axi_clk_req_rem_portid),
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.s_ctrlport_req_data (mpm_endpoint_ctrlport_axi_clk_req_data),
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.s_ctrlport_req_byte_en (mpm_endpoint_ctrlport_axi_clk_req_byte_en),
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.s_ctrlport_req_has_time (mpm_endpoint_ctrlport_axi_clk_req_has_time),
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.s_ctrlport_req_time (mpm_endpoint_ctrlport_axi_clk_req_time),
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.s_ctrlport_req_has_time (1'b0),
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.s_ctrlport_req_time (64'b0),
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.s_ctrlport_resp_ack (mpm_endpoint_ctrlport_axi_clk_resp_ack),
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.s_ctrlport_resp_status (mpm_endpoint_ctrlport_axi_clk_resp_status),
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.s_ctrlport_resp_data (mpm_endpoint_ctrlport_axi_clk_resp_data),
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.m_ctrlport_clk (ctrlport_clk),
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.m_ctrlport_req_wr (mpm_endpoint_ctrlport_pll_clk_req_wr),
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.m_ctrlport_req_rd (mpm_endpoint_ctrlport_pll_clk_req_rd),
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.m_ctrlport_req_addr (mpm_endpoint_ctrlport_pll_clk_req_addr),
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.m_ctrlport_req_wr (mpm_endpoint_ctrlport_req_wr),
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.m_ctrlport_req_rd (mpm_endpoint_ctrlport_req_rd),
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.m_ctrlport_req_addr (mpm_endpoint_ctrlport_req_addr),
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.m_ctrlport_req_portid (),
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.m_ctrlport_req_rem_epid (),
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.m_ctrlport_req_rem_portid (),
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.m_ctrlport_req_data (mpm_endpoint_ctrlport_pll_clk_req_data),
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.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_pll_clk_req_byte_en),
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.m_ctrlport_req_has_time (mpm_endpoint_ctrlport_pll_clk_req_has_time),
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.m_ctrlport_req_time (mpm_endpoint_ctrlport_pll_clk_req_time),
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.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_pll_clk_resp_ack),
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.m_ctrlport_resp_status (mpm_endpoint_ctrlport_pll_clk_resp_status),
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.m_ctrlport_resp_data (mpm_endpoint_ctrlport_pll_clk_resp_data)
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);
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// Apply time of ControlPort request to MPM endpoint request.
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wire [19:0] mpm_endpoint_ctrlport_req_addr;
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wire [ 3:0] mpm_endpoint_ctrlport_req_byte_en;
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wire [31:0] mpm_endpoint_ctrlport_req_data;
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wire mpm_endpoint_ctrlport_req_rd;
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wire mpm_endpoint_ctrlport_req_wr;
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wire mpm_endpoint_ctrlport_resp_ack;
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wire [31:0] mpm_endpoint_ctrlport_resp_data;
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wire [ 1:0] mpm_endpoint_ctrlport_resp_status;
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ctrlport_timer #(
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.EXEC_LATE_CMDS (1)
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) ctrlport_timer_mpm (
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.clk (ctrlport_clk),
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.rst (ctrlport_rst),
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.time_now (radio_time_prc),
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.time_now_stb (radio_time_stb_prc),
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.time_ignore_bits (time_ignore_bits),
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.s_ctrlport_req_wr (mpm_endpoint_ctrlport_pll_clk_req_wr),
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.s_ctrlport_req_rd (mpm_endpoint_ctrlport_pll_clk_req_rd),
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.s_ctrlport_req_addr (mpm_endpoint_ctrlport_pll_clk_req_addr),
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.s_ctrlport_req_data (mpm_endpoint_ctrlport_pll_clk_req_data),
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.s_ctrlport_req_byte_en (mpm_endpoint_ctrlport_pll_clk_req_byte_en),
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.s_ctrlport_req_has_time (mpm_endpoint_ctrlport_pll_clk_req_has_time),
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.s_ctrlport_req_time (mpm_endpoint_ctrlport_pll_clk_req_time),
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.s_ctrlport_resp_ack (mpm_endpoint_ctrlport_pll_clk_resp_ack),
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.s_ctrlport_resp_status (mpm_endpoint_ctrlport_pll_clk_resp_status),
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.s_ctrlport_resp_data (mpm_endpoint_ctrlport_pll_clk_resp_data),
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.m_ctrlport_req_wr (mpm_endpoint_ctrlport_req_wr),
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.m_ctrlport_req_rd (mpm_endpoint_ctrlport_req_rd),
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.m_ctrlport_req_addr (mpm_endpoint_ctrlport_req_addr),
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.m_ctrlport_req_data (mpm_endpoint_ctrlport_req_data),
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.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_req_byte_en),
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.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_resp_ack),
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.m_ctrlport_resp_status (mpm_endpoint_ctrlport_resp_status),
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.m_ctrlport_resp_data (mpm_endpoint_ctrlport_resp_data)
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.m_ctrlport_req_data (mpm_endpoint_ctrlport_req_data),
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.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_req_byte_en),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_resp_ack),
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.m_ctrlport_resp_status (mpm_endpoint_ctrlport_resp_status),
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.m_ctrlport_resp_data (mpm_endpoint_ctrlport_resp_data)
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);
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//---------------------------------------------------------------------------
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@@ -272,16 +202,14 @@ module cpld_interface (
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//---------------------------------------------------------------------------
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// Transfer request to pll_ref_clk domain.
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wire [19:0] app_ctrlport_pll_clk_req_addr;
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wire [ 3:0] app_ctrlport_pll_clk_req_byte_en;
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wire [31:0] app_ctrlport_pll_clk_req_data;
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wire app_ctrlport_pll_clk_req_has_time;
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wire app_ctrlport_pll_clk_req_rd;
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wire [63:0] app_ctrlport_pll_clk_req_time;
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wire app_ctrlport_pll_clk_req_wr;
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wire app_ctrlport_pll_clk_resp_ack;
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wire [31:0] app_ctrlport_pll_clk_resp_data;
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wire [ 1:0] app_ctrlport_pll_clk_resp_status;
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wire [19:0] app_ctrlport_req_addr;
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wire [ 3:0] app_ctrlport_req_byte_en;
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wire [31:0] app_ctrlport_req_data;
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wire app_ctrlport_req_rd;
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wire app_ctrlport_req_wr;
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wire app_ctrlport_resp_ack;
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wire [31:0] app_ctrlport_resp_data;
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wire [ 1:0] app_ctrlport_resp_status;
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ctrlport_clk_cross ctrlport_clk_cross_app (
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.rst (ctrlport_rst),
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@@ -294,63 +222,25 @@ module cpld_interface (
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.s_ctrlport_req_rem_portid (),
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.s_ctrlport_req_data (s_ctrlport_req_data),
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.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en),
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.s_ctrlport_req_has_time (s_ctrlport_req_has_time),
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.s_ctrlport_req_time (s_ctrlport_req_time),
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.s_ctrlport_req_has_time (1'b0),
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.s_ctrlport_req_time (64'b0),
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.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
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.s_ctrlport_resp_status (s_ctrlport_resp_status),
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.s_ctrlport_resp_data (s_ctrlport_resp_data),
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.m_ctrlport_clk (ctrlport_clk),
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.m_ctrlport_req_wr (app_ctrlport_pll_clk_req_wr),
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.m_ctrlport_req_rd (app_ctrlport_pll_clk_req_rd),
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.m_ctrlport_req_addr (app_ctrlport_pll_clk_req_addr),
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.m_ctrlport_req_wr (app_ctrlport_req_wr),
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.m_ctrlport_req_rd (app_ctrlport_req_rd),
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.m_ctrlport_req_addr (app_ctrlport_req_addr),
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.m_ctrlport_req_portid (),
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.m_ctrlport_req_rem_epid (),
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.m_ctrlport_req_rem_portid (),
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.m_ctrlport_req_data (app_ctrlport_pll_clk_req_data),
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.m_ctrlport_req_byte_en (app_ctrlport_pll_clk_req_byte_en),
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.m_ctrlport_req_has_time (app_ctrlport_pll_clk_req_has_time),
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.m_ctrlport_req_time (app_ctrlport_pll_clk_req_time),
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.m_ctrlport_resp_ack (app_ctrlport_pll_clk_resp_ack),
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.m_ctrlport_resp_status (app_ctrlport_pll_clk_resp_status),
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.m_ctrlport_resp_data (app_ctrlport_pll_clk_resp_data)
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);
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// Apply timing to application based ControlPort request.
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wire [19:0] app_ctrlport_req_addr;
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wire [ 3:0] app_ctrlport_req_byte_en;
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wire [31:0] app_ctrlport_req_data;
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wire app_ctrlport_req_rd;
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wire app_ctrlport_req_wr;
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wire app_ctrlport_resp_ack;
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wire [31:0] app_ctrlport_resp_data;
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wire [ 1:0] app_ctrlport_resp_status;
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ctrlport_timer #(
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.EXEC_LATE_CMDS (1)
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) ctrlport_timer_app (
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.clk (ctrlport_clk),
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.rst (ctrlport_rst),
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.time_now (radio_time_prc),
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.time_now_stb (radio_time_stb_prc),
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.time_ignore_bits (time_ignore_bits),
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.s_ctrlport_req_wr (app_ctrlport_pll_clk_req_wr),
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.s_ctrlport_req_rd (app_ctrlport_pll_clk_req_rd),
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.s_ctrlport_req_addr (app_ctrlport_pll_clk_req_addr),
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.s_ctrlport_req_data (app_ctrlport_pll_clk_req_data),
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.s_ctrlport_req_byte_en (app_ctrlport_pll_clk_req_byte_en),
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.s_ctrlport_req_has_time (app_ctrlport_pll_clk_req_has_time),
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.s_ctrlport_req_time (app_ctrlport_pll_clk_req_time),
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.s_ctrlport_resp_ack (app_ctrlport_pll_clk_resp_ack),
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.s_ctrlport_resp_status (app_ctrlport_pll_clk_resp_status),
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.s_ctrlport_resp_data (app_ctrlport_pll_clk_resp_data),
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.m_ctrlport_req_wr (app_ctrlport_req_wr),
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.m_ctrlport_req_rd (app_ctrlport_req_rd),
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.m_ctrlport_req_addr (app_ctrlport_req_addr),
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.m_ctrlport_req_data (app_ctrlport_req_data),
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.m_ctrlport_req_byte_en (app_ctrlport_req_byte_en),
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.m_ctrlport_resp_ack (app_ctrlport_resp_ack),
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.m_ctrlport_resp_status (app_ctrlport_resp_status),
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.m_ctrlport_resp_data (app_ctrlport_resp_data)
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.m_ctrlport_req_data (app_ctrlport_req_data),
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.m_ctrlport_req_byte_en (app_ctrlport_req_byte_en),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (app_ctrlport_resp_ack),
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.m_ctrlport_resp_status (app_ctrlport_resp_status),
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.m_ctrlport_resp_data (app_ctrlport_resp_data)
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);
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//---------------------------------------------------------------------------
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@@ -440,8 +330,8 @@ module cpld_interface (
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.s_ctrlport_req_rem_portid (),
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.s_ctrlport_req_data ({ipass_ctrlport_req_data, led_ctrlport_req_data, mpm_endpoint_ctrlport_req_data, app_ctrlport_req_data}),
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.s_ctrlport_req_byte_en ({ipass_ctrlport_req_byte_en, led_ctrlport_req_byte_en, mpm_endpoint_ctrlport_req_byte_en, app_ctrlport_req_byte_en}),
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.s_ctrlport_req_has_time (),
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.s_ctrlport_req_time (),
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.s_ctrlport_req_has_time ({4{1'b0}}),
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.s_ctrlport_req_time ({4{64'b0}}),
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.s_ctrlport_resp_ack ({ipass_ctrlport_resp_ack, led_ctrlport_resp_ack, mpm_endpoint_ctrlport_resp_ack, app_ctrlport_resp_ack}),
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.s_ctrlport_resp_status ({ipass_ctrlport_resp_status, led_ctrlport_resp_status, mpm_endpoint_ctrlport_resp_status, app_ctrlport_resp_status}),
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.s_ctrlport_resp_data ({ipass_ctrlport_resp_data, led_ctrlport_resp_data, mpm_endpoint_ctrlport_resp_data, app_ctrlport_resp_data}),
|
||||
|
||||
Reference in New Issue
Block a user