mpm/fpga: x4xx: Major updates in preparation for future devices
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
This commit is contained in:
Javier Valenzuela
committed by
Martin Braun
Martin Braun
co-authored by
Wade Fife
Ryan Marlow
Martin Braun
Humberto Jimenez
Wade Fife
Ryan Marlow
Martin Braun
Humberto Jimenez
parent
ffdcc016cc
commit
adf6f576c6
@@ -60,57 +60,9 @@ set_property IOSTANDARD DIFF_SSTL12 [get_ports {FABRIC_CLK_OUT_*}]
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# Pin constraints for the other PL pins (1.8 V)
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###############################################################################
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set_property PACKAGE_PIN F6 [get_ports {DB1_GPIO[0]}]
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set_property PACKAGE_PIN E6 [get_ports {DB1_GPIO[1]}]
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set_property PACKAGE_PIN E9 [get_ports {DB1_GPIO[2]}]
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set_property PACKAGE_PIN E8 [get_ports {DB1_GPIO[3]}]
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set_property PACKAGE_PIN E7 [get_ports {DB1_GPIO[4]}]
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set_property PACKAGE_PIN D6 [get_ports {DB1_GPIO[5]}]
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set_property PACKAGE_PIN D10 [get_ports {DB1_GPIO[6]}]
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set_property PACKAGE_PIN C10 [get_ports {DB1_GPIO[7]}]
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set_property PACKAGE_PIN C8 [get_ports {DB1_GPIO[8]}]
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set_property PACKAGE_PIN C7 [get_ports {DB1_GPIO[9]}]
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set_property PACKAGE_PIN D9 [get_ports {DB1_GPIO[10]}]
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set_property PACKAGE_PIN D8 [get_ports {DB1_GPIO[11]}]
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set_property PACKAGE_PIN B8 [get_ports {DB1_GPIO[12]}]
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set_property PACKAGE_PIN B7 [get_ports {DB1_GPIO[13]}]
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set_property PACKAGE_PIN B10 [get_ports {DB1_GPIO[14]}]
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set_property PACKAGE_PIN B9 [get_ports {DB1_GPIO[15]}]
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set_property PACKAGE_PIN C6 [get_ports {DB1_GPIO[16]}]
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set_property PACKAGE_PIN C5 [get_ports {DB1_GPIO[17]}]
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set_property PACKAGE_PIN B5 [get_ports {DB1_GPIO[18]}]
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set_property PACKAGE_PIN A5 [get_ports {DB1_GPIO[19]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[*]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[*]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[*]}]
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set_property PACKAGE_PIN A7 [get_ports {DB1_SYNTH_SYNC}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_SYNTH_SYNC}]
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set_property PACKAGE_PIN AW6 [get_ports {DB0_GPIO[0]}]
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set_property PACKAGE_PIN AW5 [get_ports {DB0_GPIO[1]}]
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set_property PACKAGE_PIN AW4 [get_ports {DB0_GPIO[2]}]
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set_property PACKAGE_PIN AW3 [get_ports {DB0_GPIO[3]}]
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set_property PACKAGE_PIN AV3 [get_ports {DB0_GPIO[4]}]
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set_property PACKAGE_PIN AV2 [get_ports {DB0_GPIO[5]}]
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set_property PACKAGE_PIN AU2 [get_ports {DB0_GPIO[6]}]
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set_property PACKAGE_PIN AU1 [get_ports {DB0_GPIO[7]}]
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set_property PACKAGE_PIN AV6 [get_ports {DB0_GPIO[8]}]
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set_property PACKAGE_PIN AV5 [get_ports {DB0_GPIO[9]}]
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set_property PACKAGE_PIN AU4 [get_ports {DB0_GPIO[10]}]
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set_property PACKAGE_PIN AU3 [get_ports {DB0_GPIO[11]}]
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set_property PACKAGE_PIN AT5 [get_ports {DB0_GPIO[12]}]
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set_property PACKAGE_PIN AU5 [get_ports {DB0_GPIO[13]}]
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set_property PACKAGE_PIN AT7 [get_ports {DB0_GPIO[14]}]
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set_property PACKAGE_PIN AT6 [get_ports {DB0_GPIO[15]}]
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set_property PACKAGE_PIN AU8 [get_ports {DB0_GPIO[16]}]
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set_property PACKAGE_PIN AV8 [get_ports {DB0_GPIO[17]}]
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set_property PACKAGE_PIN AU7 [get_ports {DB0_GPIO[18]}]
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set_property PACKAGE_PIN AV7 [get_ports {DB0_GPIO[19]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[*]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[*]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[*]}]
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set_property PACKAGE_PIN AP5 [get_ports {DB0_SYNTH_SYNC}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_SYNTH_SYNC}]
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@@ -0,0 +1,59 @@
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#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# DB GPIO pin constraints for X410.
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#
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###############################################################################
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# Pin constraints for the other PL pins (1.8 V)
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###############################################################################
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set_property PACKAGE_PIN F6 [get_ports {DB1_GPIO[0]}]
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set_property PACKAGE_PIN E6 [get_ports {DB1_GPIO[1]}]
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set_property PACKAGE_PIN E9 [get_ports {DB1_GPIO[2]}]
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set_property PACKAGE_PIN E8 [get_ports {DB1_GPIO[3]}]
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set_property PACKAGE_PIN E7 [get_ports {DB1_GPIO[4]}]
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set_property PACKAGE_PIN D6 [get_ports {DB1_GPIO[5]}]
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set_property PACKAGE_PIN D10 [get_ports {DB1_GPIO[6]}]
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set_property PACKAGE_PIN C10 [get_ports {DB1_GPIO[7]}]
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set_property PACKAGE_PIN C8 [get_ports {DB1_GPIO[8]}]
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set_property PACKAGE_PIN C7 [get_ports {DB1_GPIO[9]}]
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set_property PACKAGE_PIN D9 [get_ports {DB1_GPIO[10]}]
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set_property PACKAGE_PIN D8 [get_ports {DB1_GPIO[11]}]
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set_property PACKAGE_PIN B8 [get_ports {DB1_GPIO[12]}]
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set_property PACKAGE_PIN B7 [get_ports {DB1_GPIO[13]}]
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set_property PACKAGE_PIN B10 [get_ports {DB1_GPIO[14]}]
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set_property PACKAGE_PIN B9 [get_ports {DB1_GPIO[15]}]
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set_property PACKAGE_PIN C6 [get_ports {DB1_GPIO[16]}]
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set_property PACKAGE_PIN C5 [get_ports {DB1_GPIO[17]}]
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set_property PACKAGE_PIN B5 [get_ports {DB1_GPIO[18]}]
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set_property PACKAGE_PIN A5 [get_ports {DB1_GPIO[19]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[*]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[*]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[*]}]
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set_property PACKAGE_PIN AW6 [get_ports {DB0_GPIO[0]}]
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set_property PACKAGE_PIN AW5 [get_ports {DB0_GPIO[1]}]
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set_property PACKAGE_PIN AW4 [get_ports {DB0_GPIO[2]}]
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set_property PACKAGE_PIN AW3 [get_ports {DB0_GPIO[3]}]
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set_property PACKAGE_PIN AV3 [get_ports {DB0_GPIO[4]}]
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set_property PACKAGE_PIN AV2 [get_ports {DB0_GPIO[5]}]
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set_property PACKAGE_PIN AU2 [get_ports {DB0_GPIO[6]}]
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set_property PACKAGE_PIN AU1 [get_ports {DB0_GPIO[7]}]
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set_property PACKAGE_PIN AV6 [get_ports {DB0_GPIO[8]}]
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set_property PACKAGE_PIN AV5 [get_ports {DB0_GPIO[9]}]
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set_property PACKAGE_PIN AU4 [get_ports {DB0_GPIO[10]}]
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set_property PACKAGE_PIN AU3 [get_ports {DB0_GPIO[11]}]
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set_property PACKAGE_PIN AT5 [get_ports {DB0_GPIO[12]}]
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set_property PACKAGE_PIN AU5 [get_ports {DB0_GPIO[13]}]
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set_property PACKAGE_PIN AT7 [get_ports {DB0_GPIO[14]}]
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set_property PACKAGE_PIN AT6 [get_ports {DB0_GPIO[15]}]
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set_property PACKAGE_PIN AU8 [get_ports {DB0_GPIO[16]}]
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set_property PACKAGE_PIN AV8 [get_ports {DB0_GPIO[17]}]
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set_property PACKAGE_PIN AU7 [get_ports {DB0_GPIO[18]}]
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set_property PACKAGE_PIN AV7 [get_ports {DB0_GPIO[19]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[*]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[*]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[*]}]
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@@ -16,12 +16,6 @@
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set ref_clk_period 40.00
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create_clock -name ref_clk -period $ref_clk_period [get_ports BASE_REFCLK_FPGA_P]
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# PLL Reference Clock. Used to derive data clocks.
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# Constrain to the fastest possible clock rate supported in the driver.
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# MPM supports 61.44 / 62.5 / 64.0 MHz.
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set pll_ref_clk_period 15.625
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create_clock -name pll_ref_clk -period $pll_ref_clk_period [get_ports PLL_REFCLK_FPGA_P]
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# MGT Clocks
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# Clock Reference | Frequency | Purpose
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# MGT_REFCLK_LMK0 | 156.25/125 MHz | 10 GbE
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@@ -69,22 +63,11 @@ set synth_sync_ports [get_ports {DB0_SYNTH_SYNC DB1_SYNTH_SYNC}]
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set_output_delay -clock [get_clocks pll_ref_clk] -min -$synth_sync_hold_requirement $synth_sync_ports
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set_output_delay -clock [get_clocks pll_ref_clk] -max $synth_sync_setup_requirement $synth_sync_ports
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###############################################################################
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# SPI to MB CPLD (PL)
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# This interface is defined as system synchronous to pll_ref_clk.
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###############################################################################
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# The output delays are chosen to allow a large time window of valid data for
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# the MB CPLD logic.
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set spi_min_out_delay 0.000
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set spi_max_out_delay 11.000
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# Set output constraints for all ports.
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set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]
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set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports
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set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports
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# Both CPLD and FPGA use PLL reference clock from a common clock chip.
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# The traces from that clock chip to the ICs are not length matched. Assume a
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# worst case clock difference of 0.5 ns at the IC inputs. There is no direction
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@@ -249,93 +232,6 @@ set_output_delay -clock ref_clk -max $lmk_sync_output_max_delay [get_ports {LMK_
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set_output_delay -clock ref_clk -min $lmk_sync_output_min_delay [get_ports {LMK_SYNC}]
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###############################################################################
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# SPLL SYSREF Capture
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###############################################################################
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# SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces
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# the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both
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# SYSREF and PLL reference clock are directly fed into the RFSoC.
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# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC
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# output) with a double synchronizer and then transfered to the RFDC clock
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# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for
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# sync. purposes.
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# SYSREF is a continuous signal running at PRC freq. / 25, and it is
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# intentionally shifted in the LMK chip to align it closer to the
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# PRC's falling edge.
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# The added delay follows the formula:
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# SYSREF LMK delay = 22 * sample clock period
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# The highest sampling frequency supported in MPM (3.072 GHz) is used for
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# timing constrains. Therefore, SYSREF LMK's delay = 22 * (1 / 3.072e9).
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set sysref_lmk_delay 7.161
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#
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# These are the signals' lengths and corresponding delays (assuming 170 ps/in):
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# - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns
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# - PRC --> 5668 mils (5.668 inches) = 0.964 ns
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#
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# For min/max input delay calculations, it is assumed min prop. delay of 0 ns,
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# which essentially over-constrains SYSREF.
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#
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# The max input delay is the latest that SYSREF may arrive w.r.t PRC, and it is
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# calculated as follows:
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# Input delay (max) = SYSREF's LMK delay + SYSREF prop. delay (max)
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# - PRC prop. delay (min)
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set sysref_max_input_delay [expr {$sysref_lmk_delay + 0.985 - 0}]
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#
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# The min input delay is the earliest that SYSREF may arrive w.r.t PRC, and it
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# is calculated as follows:
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# Input delay (min) = SYSREF's LMK delay + SYSREF prop. delay (min)
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# - PRC prop. delay (min)
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set sysref_min_input_delay [expr {$sysref_lmk_delay + 0 - 0.964}]
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set_input_delay -clock pll_ref_clk -max $sysref_max_input_delay [get_ports {SYSREF_FABRIC_P}]
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set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSREF_FABRIC_P}]
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###############################################################################
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# DB GPIO
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# This interface is defined as system synchronous to pll_ref_clk.
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# Some timing constants in this section are declared in
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# <repo>/fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc
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###############################################################################
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# Set output constraints for all ports.
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set db_gpio_ports [get_ports {DB0_GPIO[*] DB1_GPIO[*]}]
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set_output_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_fpga_min_out $db_gpio_ports
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set_output_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_fpga_max_out $db_gpio_ports
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# Output enable signal is available one clock cycle ahead of valid data, this
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# enables the use of multi-cycle paths.
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set db_gpio_out_en_regs [get_cells -hierarchical -filter \
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{PRIMITIVE_TYPE =~ REGISTER.*.* && NAME =~ "*bytestream_output_enable*"}]
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set_multicycle_path 2 -setup -from $db_gpio_out_en_regs -to $db_gpio_ports
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set_multicycle_path 1 -hold -from $db_gpio_out_en_regs -to $db_gpio_ports
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# Calculate output delays back from capturing edge, add board delay and clock
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# difference.
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# Assume worst case as data being generated late and receiving an early clock:
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# - Max CPLD TCO
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# - Max data propagation delay
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# - Max CPLD clock propagation delay and minimum FPGA clock propagation delay
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# - Maximum delay from MC100EPT23 clock buffer
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set_input_delay -clock pll_ref_clk \
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-max [expr {$pll_ref_clk_period - $db_gpio_cpld_max_out + $db_gpio_board_max_delay \
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+ $db_cpld_prc_clock_prop_max - $fpga_prc_clock_prop_min + $clock_translate_max}] \
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$db_gpio_ports
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# Negate minimum output delay as it is defined from the change to the start
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# clock edge.
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# Assume worst case as data being generated early and receiving an late clock:
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# - Min CPLD TCO
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# - Min data propagation delay (0)
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# - Min CPLD clock propagation delay and max FPGA clock propagation delay
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set_input_delay -clock pll_ref_clk \
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-min [expr {- $db_gpio_cpld_min_out \
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- $db_gpio_board_min_delay \
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- $db_cpld_prc_clock_prop_min + $fpga_prc_clock_prop_max}] \
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$db_gpio_ports
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###############################################################################
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# x4xx_ps_rfdc_bd
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###############################################################################
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@@ -350,32 +246,6 @@ set gpio_regs [get_pins -of [get_cells -filter {IS_SEQUENTIAL && NAME =~ *rfdc/c
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set mux_regs [get_cells -hier -filter {IS_SEQUENTIAL && NAME =~ *rfdc/calibration_muxes/gpio_to_axis_mux*}]
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set_false_path -from $gpio_regs -to $mux_regs
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# This property tells Vivado that we require these clocks to be well aligned.
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# We have synchronous clock domain crossings between these clocks that can have
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# large hold violations after placement due to uneven clock loading.
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set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk_2x ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk \
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}]
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# We treat rfdc_clk and data_clk buffers as asynchronous, with knowledge that
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# code clocked in this domain will be reset after this clocked is enabled. This
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# will make timing easier to meet on these clock domains.
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set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg1x*/C}] \
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-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_1x_buf/*BUFGCE*/CE}]
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set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg2x*/C}] \
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-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_2x_buf/*BUFGCE*/CE}]
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set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg1x*/C}] \
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-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk1xSafeBufg/CE}]
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set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg2x*/C}] \
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-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk2xSafeBufg/CE}]
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###############################################################################
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# Misc Constraints
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@@ -0,0 +1,141 @@
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#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# Timing constraints exclusive to X410. These should be used
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# in conjunction with ./common.xdc
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#
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###############################################################################
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# DB GPIO
|
||||
# This interface is defined as system synchronous to pll_ref_clk.
|
||||
# Some timing constants in this section are declared in
|
||||
# <repo>/fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc
|
||||
###############################################################################
|
||||
|
||||
# Set output constraints for all ports.
|
||||
set db_gpio_ports [get_ports {DB0_GPIO[*] DB1_GPIO[*]}]
|
||||
set_output_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_fpga_min_out $db_gpio_ports
|
||||
set_output_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_fpga_max_out $db_gpio_ports
|
||||
|
||||
# Output enable signal is available one clock cycle ahead of valid data, this
|
||||
# enables the use of multi-cycle paths.
|
||||
set db_gpio_out_en_regs [get_cells -hierarchical -filter \
|
||||
{PRIMITIVE_TYPE =~ REGISTER.*.* && NAME =~ "*bytestream_output_enable*"}]
|
||||
set_multicycle_path 2 -setup -from $db_gpio_out_en_regs -to $db_gpio_ports
|
||||
set_multicycle_path 1 -hold -from $db_gpio_out_en_regs -to $db_gpio_ports
|
||||
|
||||
# Calculate output delays back from capturing edge, add board delay and clock
|
||||
# difference.
|
||||
# Assume worst case as data being generated late and receiving an early clock:
|
||||
# - Max CPLD TCO
|
||||
# - Max data propagation delay
|
||||
# - Max CPLD clock propagation delay and minimum FPGA clock propagation delay
|
||||
# - Maximum delay from MC100EPT23 clock buffer
|
||||
set_input_delay -clock pll_ref_clk \
|
||||
-max [expr {$pll_ref_clk_period - $db_gpio_cpld_max_out + $db_gpio_board_max_delay \
|
||||
+ $db_cpld_prc_clock_prop_max - $fpga_prc_clock_prop_min + $clock_translate_max}] \
|
||||
$db_gpio_ports
|
||||
|
||||
# Negate minimum output delay as it is defined from the change to the start
|
||||
# clock edge.
|
||||
# Assume worst case as data being generated early and receiving an late clock:
|
||||
# - Min CPLD TCO
|
||||
# - Min data propagation delay (0)
|
||||
# - Min CPLD clock propagation delay and max FPGA clock propagation delay
|
||||
set_input_delay -clock pll_ref_clk \
|
||||
-min [expr {- $db_gpio_cpld_min_out \
|
||||
- $db_gpio_board_min_delay \
|
||||
- $db_cpld_prc_clock_prop_min + $fpga_prc_clock_prop_max}] \
|
||||
$db_gpio_ports
|
||||
|
||||
|
||||
###############################################################################
|
||||
# x410_ps_rfdc_bd
|
||||
###############################################################################
|
||||
|
||||
# This property tells Vivado that we require these clocks to be well aligned.
|
||||
# We have synchronous clock domain crossings between these clocks that can have
|
||||
# large hold violations after placement due to uneven clock loading.
|
||||
set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\
|
||||
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\
|
||||
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\
|
||||
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\
|
||||
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk_2x ||\
|
||||
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk \
|
||||
}]
|
||||
|
||||
# We treat rfdc_clk and data_clk buffers as asynchronous, with knowledge that
|
||||
# code clocked in this domain will be reset after this clocked is enabled. This
|
||||
# will make timing easier to meet on these clock domains.
|
||||
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg1x*/C}] \
|
||||
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_1x_buf/*BUFGCE*/CE}]
|
||||
|
||||
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg2x*/C}] \
|
||||
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_2x_buf/*BUFGCE*/CE}]
|
||||
|
||||
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg1x*/C}] \
|
||||
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk1xSafeBufg/CE}]
|
||||
|
||||
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg2x*/C}] \
|
||||
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk2xSafeBufg/CE}]
|
||||
|
||||
|
||||
###############################################################################
|
||||
# SPLL SYSREF Capture
|
||||
###############################################################################
|
||||
|
||||
# SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces
|
||||
# the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both
|
||||
# SYSREF and PLL reference clock are directly fed into the RFSoC.
|
||||
# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC
|
||||
# output) with a double synchronizer and then transfered to the RFDC clock
|
||||
# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for
|
||||
# sync. purposes.
|
||||
# SYSREF is a continuous signal running at PRC freq. / 25, and it is
|
||||
# intentionally shifted in the LMK chip to align it closer to the
|
||||
# PRC's falling edge.
|
||||
# The added delay follows the formula:
|
||||
# SYSREF LMK delay = 22 * sample clock period
|
||||
# The highest sampling frequency supported in MPM (3.072 GHz) is used for
|
||||
# timing constraints. Therefore, SYSREF LMK's delay = 22 * (1 / 3.072e9).
|
||||
set sysref_lmk_delay 7.161
|
||||
#
|
||||
# These are the signals' lengths and corresponding delays (assuming 170 ps/in):
|
||||
# - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns
|
||||
# - PRC --> 5668 mils (5.668 inches) = 0.964 ns
|
||||
#
|
||||
# For min/max input delay calculations, it is assumed min prop. delay of 0 ns,
|
||||
# which essentially over-constrains SYSREF.
|
||||
#
|
||||
# The max input delay is the latest that SYSREF may arrive w.r.t PRC, and it is
|
||||
# calculated as follows:
|
||||
# Input delay (max) = SYSREF's LMK delay + SYSREF prop. delay (max)
|
||||
# - PRC prop. delay (min)
|
||||
set sysref_max_input_delay [expr {$sysref_lmk_delay + 0.985 - 0}]
|
||||
#
|
||||
# The min input delay is the earliest that SYSREF may arrive w.r.t PRC, and it
|
||||
# is calculated as follows:
|
||||
# Input delay (min) = SYSREF's LMK delay + SYSREF prop. delay (min)
|
||||
# - PRC prop. delay (min)
|
||||
set sysref_min_input_delay [expr {$sysref_lmk_delay + 0 - 0.964}]
|
||||
|
||||
set_input_delay -clock pll_ref_clk -max $sysref_max_input_delay [get_ports {SYSREF_FABRIC_P}]
|
||||
set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSREF_FABRIC_P}]
|
||||
|
||||
###############################################################################
|
||||
# SPI to MB CPLD (PL)
|
||||
# This interface is defined as system synchronous to pll_ref_clk.
|
||||
###############################################################################
|
||||
|
||||
# The output delays are chosen to allow a large time window of valid data for
|
||||
# the MB CPLD logic.
|
||||
set spi_min_out_delay 0.000
|
||||
set spi_max_out_delay 11.000
|
||||
|
||||
# Set output constraints for all ports.
|
||||
set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]
|
||||
set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports
|
||||
set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports
|
||||
@@ -0,0 +1,18 @@
|
||||
#
|
||||
# Copyright 2022 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
# Description:
|
||||
# Clock definition constraints for X410
|
||||
#
|
||||
|
||||
###############################################################################
|
||||
# Motherboard Clocks
|
||||
###############################################################################
|
||||
|
||||
# PLL Reference Clock. Used to derive data clocks.
|
||||
# Constrain to the fastest possible clock rate supported in the driver.
|
||||
# MPM supports 61.44 / 62.5 / 64.0 MHz.
|
||||
set pll_ref_clk_period 15.625
|
||||
create_clock -name pll_ref_clk -period $pll_ref_clk_period [get_ports PLL_REFCLK_FPGA_P]
|
||||
Reference in New Issue
Block a user