mpm/fpga: x4xx: Major updates in preparation for future devices

FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223

top/x400/Makefile.x4xx.inc

@@ -35,6 +35,7 @@ include $(LIB_DIR)/dsp/Makefile.srcs
 include $(LIB_DIR)/ip/Makefile.inc
 include $(LIB_DIR)/rfnoc/Makefile.srcs
 include $(LIB_DIR)/wb_spi/Makefile.srcs
+include $(LIB_DIR)/wishbone/Makefile.srcs
 include $(LIB_DIR)/axi4_sv/Makefile.srcs
 include $(LIB_DIR)/axi4s_sv/Makefile.srcs
 include $(LIB_DIR)/axi4lite_sv/Makefile.srcs
@@ -62,10 +63,7 @@ EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
 ##################################################
 # Sources
 ##################################################
-TOP_SRCS =
-
-ifdef X410
-TOP_SRCS += \
+TOP_SRCS = \
 x4xx.v \
 x4xx_qsfp_wrapper_temp.sv \
 x4xx_qsfp_wrapper.sv \
@@ -78,12 +76,6 @@ x4xx_dio.v \
 x4xx_gpio_atr.v \
 x4xx_gpio_spi.v \
 x4xx_dram.v \
-rf/100m/rf_core_100m.v \
-rf/200m/rf_core_200m.v \
-rf/200m/rf_down_4to2.v \
-rf/200m/rf_up_2to4.v \
-rf/400m/rf_core_400m.v \
-rf/common/rf_reset_controller.vhd \
 ctrlport_spi_master.v \
 cpld_interface.v \
 cpld_interface_regs.v \
@@ -92,20 +84,41 @@ rfdc_timing_control.v \
 x4xx_pps_sync.v \
 ../../lib/timing/pps_generator.v \
 dboards/ctrlport_byte_serializer.v \
-dboards/db_gpio_interface.v \
+dboards/ctrlport_clk_crossing_derived.v \
 dboards/db_gpio_reordering.v \
 ipass_present_controller.v \
 $(IMAGE_CORE)
+
+ifdef X410
+TOP_SRCS += \
+rf/100m/rf_core_100m.v \
+rf/200m/rf_core_200m.v \
+rf/200m/rf_down_4to2.v \
+rf/200m/rf_up_2to4.v \
+rf/400m/rf_core_400m.v \
+rf/x410/x410_rf_reset_controller.vhd \
+dboards/zbx/db_gpio_interface.v
 endif
 
-MB_XDC = \
+ifdef X410
+MB_XDC += \
+constraints/timing/x410_clocks.xdc
+endif
+
+MB_XDC += \
 constraints/pins/common.xdc \
-constraints/pins/rfdc_2x2.xdc \
 constraints/timing/shared_constants.sdc \
 constraints/timing/common.xdc \
 constraints/pins/dram.xdc \
 constraints/timing/dram.xdc
 
+ifdef X410
+MB_XDC += \
+constraints/pins/rfdc_2x2.xdc \
+constraints/pins/x410/db_gpio.xdc \
+constraints/timing/x410.xdc
+endif
+
 # Definitions
 # MGT Types from x4xx_mgt_type.vh
 MGT_100GbE   = 5
@@ -145,9 +158,7 @@ ifneq (,$(findstring QSFP1_3,$(EXTRA_DEFS)))
   MB_XDC += constraints/pins/qsfp1_3.xdc
 endif
 
-ifdef X410
 DESIGN_SRCS = $(abspath $(MB_XDC))
-endif
 
 # The XDC files must be read in a specific order, motherboard first and then daughterboard.
 # Outside of that, all the other sources can be read in any order desired.