mpm/fpga: x4xx: Major updates in preparation for future devices
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
This commit is contained in:
Javier Valenzuela
committed by
Martin Braun
Martin Braun
co-authored by
Wade Fife
Ryan Marlow
Martin Braun
Humberto Jimenez
Wade Fife
Ryan Marlow
Martin Braun
Humberto Jimenez
parent
ffdcc016cc
commit
adf6f576c6
+51
-52
@@ -42,26 +42,26 @@ QSFP1_4X10GBE = QSFP1_0=$(MGT_10GbE) QSFP1_1=$(MGT_10GbE) QSFP1_2=$(MGT_10Gb
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QSFP1_100GBE = QSFP1_0=$(MGT_100GbE) QSFP1_1=$(MGT_Disabled) QSFP1_2=$(MGT_Disabled) QSFP1_3=$(MGT_Disabled)
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# Target specific variables
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X410_IP: DEFS += $(QSFP0_10GBE) RFBW_100M=1
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X410_X1_100: DEFS += $(QSFP0_10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_100: DEFS += $(QSFP0_4X10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_100M=1 DRAM_CH=0
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X410_C1_100: DEFS += $(QSFP0_100GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_UC_100: DEFS += $(QSFP1_100GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_C1_200: DEFS += $(QSFP0_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_UC_200: DEFS += $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_CG_200: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X1_200: DEFS += $(QSFP0_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_200: DEFS += $(QSFP0_4X10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=0
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X410_X1_400: DEFS += $(QSFP0_10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_X4_400: DEFS += $(QSFP0_4X10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_C1_400: DEFS += $(QSFP0_100GBE) RFBW_400M=1 DRAM_CH=0
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X410_UC_400: DEFS += $(QSFP1_100GBE) RFBW_400M=1 DRAM_CH=0
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X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_400M=1 DRAM_CH=0
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X410_IP: DEFS += $(QSFP0_10GBE) RF_BW=100
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X410_X1_100: DEFS += $(QSFP0_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_100: DEFS += $(QSFP0_4X10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=0
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X410_C1_100: DEFS += $(QSFP0_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_UC_100: DEFS += $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_C1_200: DEFS += $(QSFP0_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_UC_200: DEFS += $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_CG_200: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X1_200: DEFS += $(QSFP0_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=0
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X410_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X410_UC_400: DEFS += $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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# DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to
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# exclude it. Note that some targets exclude it regardless of this setting.
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@@ -78,8 +78,7 @@ X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core
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X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_x4c_200_static_router.hex)
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X410_CG_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_cg_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_cg_200_static_router.hex)
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X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
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X410_400_128_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_128_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_128_static_router.hex)
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X410_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_d_static_router.hex)
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# Option to stop after RTL elaboration. Use this flag as a synthesis check.
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ifndef TARGET
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@@ -112,27 +111,27 @@ endif
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##
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##Available Targets
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##-------------|-----------|-----------------|-----------------|------------
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##Target | Bandwidth | QSFP0 | QSFP1 | DRAM
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##-------------|-----------|-----------------|-----------------|------------
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##X410_X1_100 | 100 MHz | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
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##X410_XG_100 | 100 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
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##X410_X4_100 | 100 MHz | 4 x 10 GbE | Unused | 64b x 4 Ch
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##X410_X4C_100 | 100 MHz | 4 x 10 GbE | 100 GbE | Unused
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##X410_C1_100 | 100 MHz | 100 GbE | Unused | 64b x 4 Ch
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##X410_UC_100 | 100 MHz | Unused | 100 GbE | 64b x 4 Ch
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##X410_X1_200 | 200 MHz | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
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##X410_XG_200 | 200 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
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##X410_X4_200 | 200 MHz | 4 x 10 GbE | Unused | 64b x 4 Ch
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##X410_X4C_200 | 200 MHz | 4 x 10 GbE | 100 GbE | Unused
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##X410_C1_200 | 200 MHz | 100 GbE | Unused | 64b x 4 Ch
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##X410_UC_200 | 200 MHz | Unused | 100 GbE | 64b x 4 Ch
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##X410_X1_400 | 400 MHz | 10 GbE (Lane 0) | Unused | 128b x 4 Ch
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##X410_XG_400 | 400 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch
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##X410_X4_400 | 400 MHz | 4 x 10 GbE | Unused | 128b x 4 Ch
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##X410_C1_400 | 400 MHz | 100 GbE | Unused | Unused
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##X410_UC_400 | 400 MHz | Unused | 100 GbE | Unused
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##X410_CG_400 | 400 MHz | 100 GbE | 100 GbE | Unused
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##-------------|-----------|----|-----------------|-----------------|------------
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##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
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##-------------|-----------|----|-----------------|-----------------|------------
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##X410_X1_100 | 100 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
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##X410_XG_100 | 100 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
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##X410_X4_100 | 100 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
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##X410_X4C_100 | 100 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused
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##X410_C1_100 | 100 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch
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##X410_UC_100 | 100 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
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##X410_X1_200 | 200 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
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##X410_XG_200 | 200 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
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##X410_X4_200 | 200 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
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##X410_X4C_200 | 200 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused
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##X410_C1_200 | 200 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch
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##X410_UC_200 | 200 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
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##X410_X1_400 | 400 MHz | 4 | 10 GbE (Lane 0) | Unused | 128b x 4 Ch
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##X410_XG_400 | 400 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch
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##X410_X4_400 | 400 MHz | 4 | 4 x 10 GbE | Unused | 128b x 4 Ch
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##X410_C1_400 | 400 MHz | 4 | 100 GbE | Unused | Unused
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##X410_UC_400 | 400 MHz | 4 | Unused | 100 GbE | Unused
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##X410_CG_400 | 400 MHz | 4 | 100 GbE | 100 GbE | Unused
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##* Note: Not all targets are shipped with UHD.
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##* Note: Some YAML configurations might not use all available DRAM channels.
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@@ -185,15 +184,15 @@ X410_UC_200: X410_IP build/usrp_x410_fpga_UC_200.dts
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$(call post_build,X410,UC_200)
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X410_X1_400: X410_IP build/usrp_x410_fpga_X1_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
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$(call post_build,X410,X1_400)
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X410_XG_400: X410_IP build/usrp_x410_fpga_XG_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
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$(call post_build,X410,XG_400)
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X410_X4_400: X410_IP build/usrp_x410_fpga_X4_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
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$(call post_build,X410,X4_400)
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X410_C1_400: X410_IP build/usrp_x410_fpga_C1_400.dts
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@@ -210,10 +209,10 @@ X410_CG_400: X410_IP build/usrp_x410_fpga_CG_400.dts
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##
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##Experimental Targets
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##-------------|-----------|-----------------|-----------------|------------
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##Target | Bandwidth | QSFP0 | QSFP1 | DRAM
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##-------------|-----------|-----------------|-----------------|------------
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##X410_CG_200 | 200 | 100 GbE | 100 GbE | 64b x 4 Ch
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##-------------|-----------|----|-----------------|-----------------|------------
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##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
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##-------------|-----------|----|-----------------|-----------------|------------
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##X410_CG_200 | 200 | 4 | 100 GbE | 100 GbE | 64b x 4 Ch
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X410_CG_200: X410_IP build/usrp_x410_fpga_CG_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
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@@ -230,10 +229,10 @@ all: X410_X4_200 X410_CG_400 X410_UC_200 ##(Default targets)
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X410_IP: ##Build IP only.
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+$(call vivado_ip,X410,$(DEFS) X410=1)
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build/%.dts: dts/*.dts dts/*.dtsi
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build/usrp_x410%.dts: dts/*.dts dts/*.dtsi
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-mkdir -p build
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tools/parse_versions_for_dts.py \
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--input regmap/versioning_regs_regmap_utils.vh \
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--input regmap/x410/versioning_regs_regmap_utils.vh \
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--output dts/x410-version-info.dtsi \
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--components fpga,cpld_ifc,db_gpio_ifc,rf_core_100m,rf_core_400m
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${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
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