mpm/fpga: x4xx: Major updates in preparation for future devices
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
This commit is contained in:
Javier Valenzuela
committed by
Martin Braun
Martin Braun
co-authored by
Wade Fife
Ryan Marlow
Martin Braun
Humberto Jimenez
Wade Fife
Ryan Marlow
Martin Braun
Humberto Jimenez
parent
ffdcc016cc
commit
adf6f576c6
@@ -0,0 +1,165 @@
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#
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# Copyright 2022 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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""" Vivado IP sub-core re-targeting.
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Script to update the sub-cores in a directory to a specific
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part number
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"""
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import argparse
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import os
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import re
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import sys
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# Parse command line options
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def get_options():
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"""Parse script arguments."""
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parser = argparse.ArgumentParser(
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description="Utility script to modify subcores for a Xilinx IP XCI file"
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)
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parser.add_argument(
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"xci_filepath", type=str, default=None, help="Name for the IP core"
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)
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parser.add_argument(
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"--target",
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type=str,
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default=None,
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help="Input value for target. Must be of the form <arch>/<device>/<package>/<speedgrade>/<silicon revision>",
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)
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parser.add_argument(
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"--name", type=str, default=None, help="Input value for new IP name"
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)
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parser.add_argument(
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"--output_dir", type=str, default=".", help="Build directory for IP"
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)
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args = parser.parse_args()
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if not args.xci_filepath:
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print("ERROR: Please specify the location for the XCI file to operate on\n")
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parser.print_help()
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sys.exit(1)
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if not os.path.isfile(args.xci_filepath):
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print(
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"ERROR: XCI File "
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+ args.xci_filepath
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+ " could not be accessed or is not a file.\n"
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)
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parser.print_help()
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sys.exit(1)
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return args
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def get_match_str(item):
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"""Produce the string to an XML parameter with a value."""
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return (
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'(.*\<spirit:configurableElementValue spirit:referenceId=".*\.'
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+ item
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+ '"\>)(.+)(\</spirit:configurableElementValue\>)'
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)
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def get_empty_match_str(item):
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"""Produce the string to an XML parameter without a value."""
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return (
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'(.*\<spirit:configurableElementValue spirit:referenceId=".*\.' + item + '")/\>'
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)
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def retarget_subcore(path, file, output_dir, target_tok):
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"""Update target parameter for the specified sub-core."""
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# Read XCI File
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with open(os.path.join(path, file)) as in_file:
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xci_lines = in_file.readlines()
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replace_dict = {
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"ARCHITECTURE": target_tok[0],
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"DEVICE": target_tok[1],
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"PACKAGE": target_tok[2],
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"SPEEDGRADE": target_tok[3],
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"C_XDEVICEFAMILY": target_tok[0],
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"C_FAMILY": target_tok[0],
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"C_XDEVICE": target_tok[1],
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}
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if len(target_tok) > 4:
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replace_dict["TEMPERATURE_GRADE"] = target_tok[4]
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if len(target_tok) > 5:
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replace_dict["SILICON_REVISION"] = target_tok[5]
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out_xci_filename = os.path.join(os.path.abspath(output_dir), os.path.basename(file))
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# Write files with modified parameters
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with open(out_xci_filename, "w") as out_file:
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for r_line in xci_lines:
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w_line = r_line
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m = re.search(
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get_match_str("(" + "|".join(list(replace_dict.keys())) + ")"), r_line
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)
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if m is not None:
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w_line = m.group(1) + replace_dict[m.group(2)] + m.group(4) + "\n"
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else:
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m = re.search(
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get_empty_match_str(
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"(" + "|".join(list(replace_dict.keys())) + ")"
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),
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r_line,
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)
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if m is not None:
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w_line = (
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m.group(1)
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+ ">"
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+ replace_dict[m.group(2)]
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+ "</spirit:configurableElementValue>\n"
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)
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out_file.write(w_line)
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def main():
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"""Perform directory traversal to detect and update sub-cores."""
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args = get_options()
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# Validate arguments
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if not os.path.isdir(args.output_dir):
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print(
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"ERROR: IP Build directory "
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+ args.output_dir
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+ " could not be accessed or is not a directory."
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)
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sys.exit(1)
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if not args.target:
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print("ERROR: No target specified.")
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sys.exit(1)
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target_tok = args.target.split("/")
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if len(target_tok) < 4:
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print(
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"ERROR: Invalid target format. Must be <arch>/<device>/<package>/<speedgrade>/<tempgrade>/<silicon revision>"
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)
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sys.exit(1)
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sub_cores = []
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# Detect sub-cores
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ip_dir, ip_name = os.path.split(args.xci_filepath)
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for path, _, files in os.walk(ip_dir):
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for name in files:
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if name.endswith("xci"):
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sub_cores.append(os.path.join(path, name))
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# Get the relative path for each IP core detected
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relative_paths = [os.path.relpath(path, ip_dir) for path in sub_cores]
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# Remove main core
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relative_paths.remove(ip_name)
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for rp in relative_paths:
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retarget_subcore(
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os.path.join(ip_dir, os.path.split(rp)[0]),
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os.path.split(rp)[1],
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os.path.join(args.output_dir, os.path.split(rp)[0]),
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target_tok,
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)
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if __name__ == "__main__":
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main()
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