mpm/fpga: x4xx: Major updates in preparation for future devices

FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223

tools/make/viv_ip_builder.mak

@@ -42,6 +42,42 @@ BUILD_VIVADO_IP = \
 	$(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) release; \
 	exit $$VIV_ERR
 
+# -------------------------------------------------------------------
+# Usage: BUILD_VIVADO_IP_WITH_SUBCORES
+# Args: $1 = IP_NAME (IP name)
+#       $2 = ARCH (zynq, kintex7, etc)
+#       $3 = PART_ID (<device>/<package>/<speedgrade>[/<tempgrade>[/<silicon revision>]])
+#       $4 = IP_SRC_DIR (Absolute path to the top level ip src dir)
+#       $5 = IP_BUILD_DIR (Absolute path to the top level ip build dir)
+#       $6 = GENERATE_EXAMPLE (0 or 1)
+# Prereqs:
+# - TOOLS_DIR must be defined globally
+# -------------------------------------------------------------------
+
+BUILD_VIVADO_IP_WITH_SUBCORES = \
+	@ \
+	echo "========================================================"; \
+	echo "BUILDER: Building IP $(1)"; \
+	echo "========================================================"; \
+	export XCI_FILE=$(call RESOLVE_PATH,$(5)/$(1)/$(1).xci); \
+	export PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \
+	export GEN_EXAMPLE=$(6); \
+	export SYNTH_IP=$(SYNTH_IP); \
+	echo "BUILDER: Staging IP in build directory..."; \
+	rm -rf $(5)/$(1); \
+	mkdir -p $(5)/$(1); \
+	$(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \
+	cp -rf $(4)/$(1)/* $(5)/$(1); \
+	echo "BUILDER: Retargeting IP to part $(2)/$(3)..."; \
+	python3 $(TOOLS_DIR)/scripts/viv_ip_xci_editor.py --output_dir=$(5)/$(1) --target=$(2)/$(3) retarget $(4)/$(1)/$(1).xci; \
+	python3 $(TOOLS_DIR)/scripts/viv_ip_retarget_subcores.py --output_dir=$(5)/$(1) --target=$(2)/$(3) $(4)/$(1)/$(1).xci; \
+	cd $(5); \
+	echo "BUILDER: Building IP..."; \
+	export VIV_ERR=0; \
+	$(TOOLS_DIR)/scripts/launch_vivado.py -mode batch -source $(call RESOLVE_PATH,$(TOOLS_DIR)/scripts/viv_generate_ip.tcl) -log $(1).log -nojournal || export VIV_ERR=$$?; \
+	$(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) release; \
+	exit $$VIV_ERR
+
 # -------------------------------------------------------------------
 # Usage: REBUILD_VIVADO_IP_WITH_PATCH
 # Args: $1 = IP_NAME (IP name)