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fpga: Multiple X300 FPGA bugfixes and enhancements

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- Fixed 10GigE firmware communication issues and sequence errors for TX
- Multiple changes to help ease timing closure
- Cleaned up build scripts
- Switched to Xilinx ISE 14.7 as the default build tool for X300


Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
This commit is contained in:
Ashish Chaudhari
2014-09-24 18:45:31 -07:00
parent 6b7004c311
commit adf2da6ac7
275 changed files with 14057 additions and 293393 deletions
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top/x300/x300_1ge.ucf
+7 -2
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@@ -1,2 +1,7 @@
NET ETH_CLK_p IOSTANDARD = LVDS_25 | LOC = L8;
NET ETH_CLK_n IOSTANDARD = LVDS_25 | LOC = L7;
NET ETH_CLK_p IOSTANDARD = LVDS_25 | LOC = L8;
NET "ETH_CLK_p" TNM_NET = ETH_CLK_p;
TIMESPEC TS_ETH_CLK_p = PERIOD "ETH_CLK_p" 8 ns HIGH 50%;
NET ETH_CLK_n IOSTANDARD = LVDS_25 | LOC = L7;
NET "ETH_CLK_n" TNM_NET = ETH_CLK_n;
TIMESPEC TS_ETH_CLK_n = PERIOD "ETH_CLK_n" TS_ETH_CLK_p HIGH 50%;