fpga: Multiple X300 FPGA bugfixes and enhancements

- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
2014-09-24 18:45:31 -07:00
parent 6b7004c311
commit adf2da6ac7
275 changed files with 14057 additions and 293393 deletions
@@ -1,2 +1,7 @@
-NET   XG_CLK_p              IOSTANDARD = LVDS_25 | LOC  =  R8;
-NET   XG_CLK_n              IOSTANDARD = LVDS_25 | LOC  =  R7;
+NET   XG_CLK_p IOSTANDARD = LVDS_25 | LOC = R8;
+NET "XG_CLK_p" TNM_NET = XG_CLK_p;
+TIMESPEC TS_XG_CLK_p = PERIOD "XG_CLK_p" 6400 ps HIGH 50%;
+
+NET   XG_CLK_n IOSTANDARD = LVDS_25 | LOC = R7;
+NET "XG_CLK_n" TNM_NET = XG_CLK_n;
+TIMESPEC TS_XG_CLK_n = PERIOD "XG_CLK_n" TS_XG_CLK_p HIGH 50%;