fpga: Multiple X300 FPGA bugfixes and enhancements
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
This commit is contained in:
Ashish Chaudhari
@@ -0,0 +1 @@
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The files in this directory have been adapted from the "Ten Gigabit EthernetPCS/PMA or SGMII (10GBASE-R/KR)" Xilinx IPCore example design.
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@@ -0,0 +1,131 @@
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// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
`timescale 1ns / 1ps
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||||
//***********************************Entity Declaration*******************************
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module ten_gig_eth_pcs_pma_GT_USRCLK_SOURCE
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(
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// IJB. Remove IBUFDS_GTE2 from 10G PHY hierarchy so that it can be shared.
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//
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||||
//input wire Q1_CLK0_GTREFCLK_PAD_N_IN,
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//input wire Q1_CLK0_GTREFCLK_PAD_P_IN,
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//output wire Q1_CLK0_GTREFCLK_OUT,
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output GT0_TXUSRCLK_OUT,
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output GT0_TXUSRCLK2_OUT,
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input GT0_TXOUTCLK_IN,
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output GT0_RXUSRCLK_OUT,
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output GT0_RXUSRCLK2_OUT,
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input GT0_RXOUTCLK_IN,
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input DRPCLK_IN,
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output DRPCLK_OUT
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);
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||||
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`define DLY #1
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||||
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//*********************************Wire Declarations**********************************
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wire tied_to_ground_i;
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wire tied_to_vcc_i;
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wire gt0_txoutclk_i;
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wire gt0_rxoutclk_i;
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// wire q1_clk0_gtrefclk;
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wire gt0_txusrclk_i;
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wire gt0_rxusrclk_i;
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//*********************************** Beginning of Code *******************************
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// Static signal Assigments
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assign tied_to_ground_i = 1'b0;
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assign tied_to_vcc_i = 1'b1;
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assign gt0_txoutclk_i = GT0_TXOUTCLK_IN;
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assign gt0_rxoutclk_i = GT0_RXOUTCLK_IN;
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// assign Q1_CLK0_GTREFCLK_OUT = q1_clk0_gtrefclk;
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//IBUFDS_GTE2
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/* -----\/----- EXCLUDED -----\/-----
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IBUFDS_GTE2 ibufds_instQ1_CLK0
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||||
(
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.O (q1_clk0_gtrefclk),
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||||
.ODIV2 (),
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||||
.CEB (tied_to_ground_i),
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.I (Q1_CLK0_GTREFCLK_PAD_P_IN),
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||||
.IB (Q1_CLK0_GTREFCLK_PAD_N_IN)
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||||
);
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||||
-----/\----- EXCLUDED -----/\----- */
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BUFG txoutclk_bufg0_i
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(
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.I (gt0_txoutclk_i),
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.O (gt0_txusrclk_i)
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||||
);
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||||
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||||
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BUFG rxoutclk_bufg1_i
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||||
(
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||||
.I (gt0_rxoutclk_i),
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.O (gt0_rxusrclk_i)
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||||
);
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||||
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||||
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||||
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||||
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assign GT0_TXUSRCLK_OUT = gt0_txusrclk_i;
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assign GT0_TXUSRCLK2_OUT = gt0_txusrclk_i;
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assign GT0_RXUSRCLK_OUT = gt0_rxusrclk_i;
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assign GT0_RXUSRCLK2_OUT = gt0_rxusrclk_i;
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endmodule
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@@ -0,0 +1,367 @@
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// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
`timescale 1ns / 1ps
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`define DLY #1
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//***************************** Entity Declaration ****************************
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module ten_gig_eth_pcs_pma_gtwizard_10gbaser #
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(
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// Simulation attributes
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parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false", // Set to "true" to speed up sim reset
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parameter RX_DFE_KL_CFG2_IN = 32'h3010D90C,
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parameter PMA_RSV_IN = 32'h001E7080,
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parameter SIM_VERSION = "4.0"
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)
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(
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//_________________________________________________________________________
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//_________________________________________________________________________
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//GT0 (X0Y0)
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//____________________________CHANNEL PORTS________________________________
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//-------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
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input [8:0] GT0_DRPADDR_IN,
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input GT0_DRPCLK_IN,
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input [15:0] GT0_DRPDI_IN,
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output [15:0] GT0_DRPDO_OUT,
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input GT0_DRPEN_IN,
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output GT0_DRPRDY_OUT,
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input GT0_DRPWE_IN,
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//----------------------------- Eye Scan Ports -----------------------------
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output GT0_EYESCANDATAERROR_OUT,
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//---------------------- Loopback and Powerdown Ports ----------------------
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input [2:0] GT0_LOOPBACK_IN,
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//----------------------------- Receive Ports ------------------------------
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input GT0_RXUSERRDY_IN,
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//------------ Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
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output GT0_RXDATAVALID_OUT,
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input GT0_RXGEARBOXSLIP_IN,
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output [1:0] GT0_RXHEADER_OUT,
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output GT0_RXHEADERVALID_OUT,
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//--------------------- Receive Ports - PRBS Detection ---------------------
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input GT0_RXPRBSCNTRESET_IN,
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output GT0_RXPRBSERR_OUT,
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input [2:0] GT0_RXPRBSSEL_IN,
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//----------------- Receive Ports - RX Data Path interface -----------------
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input GT0_GTRXRESET_IN,
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output [31:0] GT0_RXDATA_OUT,
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output GT0_RXOUTCLK_OUT,
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input GT0_RXPCSRESET_IN,
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input GT0_RXUSRCLK_IN,
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input GT0_RXUSRCLK2_IN,
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//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
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input GT0_GTXRXN_IN,
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input GT0_GTXRXP_IN,
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output GT0_RXCDRLOCK_OUT,
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output GT0_RXELECIDLE_OUT,
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//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
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input GT0_RXBUFRESET_IN,
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output [2:0] GT0_RXBUFSTATUS_OUT,
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//---------------------- Receive Ports - RX Equalizer ----------------------
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input GT0_RXLPMEN_IN,
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//---------------------- Receive Ports - RX PLL Ports ----------------------
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output GT0_RXRESETDONE_OUT,
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//----------------------------- Transmit Ports -----------------------------
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input GT0_TXUSERRDY_IN,
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//------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
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input [1:0] GT0_TXHEADER_IN,
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input [6:0] GT0_TXSEQUENCE_IN,
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//---------------- Transmit Ports - TX Data Path interface -----------------
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input GT0_GTTXRESET_IN,
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input [31:0] GT0_TXDATA_IN,
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output GT0_TXOUTCLK_OUT,
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output GT0_TXOUTCLKFABRIC_OUT,
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output GT0_TXOUTCLKPCS_OUT,
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input GT0_TXPCSRESET_IN,
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input GT0_TXUSRCLK_IN,
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input GT0_TXUSRCLK2_IN,
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//-------------- Transmit Ports - TX Driver and OOB signaling --------------
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output GT0_GTXTXN_OUT,
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output GT0_GTXTXP_OUT,
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input GT0_TXINHIBIT_IN,
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input [4:0] GT0_TXPRECURSOR_IN,
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input [4:0] GT0_TXPOSTCURSOR_IN,
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input [6:0] GT0_TXMAINCURSOR_IN,
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//--------------------- Transmit Ports - TX PLL Ports ----------------------
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output GT0_TXRESETDONE_OUT,
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//------------------- Transmit Ports - TX PRBS Generator -------------------
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input [2:0] GT0_TXPRBSSEL_IN,
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//____________________________COMMON PORTS________________________________
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//-------------------- Common Block - Ref Clock Ports ---------------------
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input GT0_GTREFCLK0_COMMON_IN,
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//----------------------- Common Block - QPLL Ports ------------------------
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output GT0_QPLLLOCK_OUT,
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input GT0_QPLLLOCKDETCLK_IN,
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output GT0_QPLLREFCLKLOST_OUT,
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input GT0_QPLLRESET_IN
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);
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//***************************** Parameter Declarations ************************
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parameter QPLL_FBDIV_TOP = 66;
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parameter QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 :
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(QPLL_FBDIV_TOP == 20) ? 10'b0000110000 :
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(QPLL_FBDIV_TOP == 32) ? 10'b0001100000 :
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(QPLL_FBDIV_TOP == 40) ? 10'b0010000000 :
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(QPLL_FBDIV_TOP == 64) ? 10'b0011100000 :
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(QPLL_FBDIV_TOP == 66) ? 10'b0101000000 :
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(QPLL_FBDIV_TOP == 80) ? 10'b0100100000 :
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(QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000;
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parameter QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 :
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(QPLL_FBDIV_TOP == 20) ? 1'b1 :
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(QPLL_FBDIV_TOP == 32) ? 1'b1 :
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(QPLL_FBDIV_TOP == 40) ? 1'b1 :
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(QPLL_FBDIV_TOP == 64) ? 1'b1 :
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(QPLL_FBDIV_TOP == 66) ? 1'b0 :
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(QPLL_FBDIV_TOP == 80) ? 1'b1 :
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(QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1;
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//***************************** Wire Declarations *****************************
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// ground and vcc signals
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wire tied_to_ground_i;
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wire [63:0] tied_to_ground_vec_i;
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wire tied_to_vcc_i;
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wire [63:0] tied_to_vcc_vec_i;
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wire gt0_qplloutclk_i;
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wire gt0_qplloutrefclk_i;
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wire gt0_qpllclk_i;
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wire gt0_qpllrefclk_i;
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||||
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||||
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//********************************* Main Body of Code**************************
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||||
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assign tied_to_ground_i = 1'b0;
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assign tied_to_ground_vec_i = 64'h0000000000000000;
|
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assign tied_to_vcc_i = 1'b1;
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assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
|
||||
|
||||
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||||
assign gt0_qpllclk_i = gt0_qplloutclk_i;
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||||
assign gt0_qpllrefclk_i = gt0_qplloutrefclk_i;
|
||||
|
||||
|
||||
//------------------------- GT Instances -------------------------------
|
||||
//_________________________________________________________________________
|
||||
//_________________________________________________________________________
|
||||
//GT0 (X0Y0)
|
||||
|
||||
ten_gig_eth_pcs_pma_gtwizard_10gbaser_GT #
|
||||
(
|
||||
// Simulation attributes
|
||||
.GT_SIM_GTRESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
|
||||
.SIM_VERSION (SIM_VERSION),
|
||||
.RX_DFE_KL_CFG2_IN (RX_DFE_KL_CFG2_IN),
|
||||
.PCS_RSVD_ATTR_IN (48'h000000000000),
|
||||
.PMA_RSV_IN (PMA_RSV_IN)
|
||||
)
|
||||
gt0_gtwizard_10gbaser_i
|
||||
(
|
||||
//-------------------------------- Channel ---------------------------------
|
||||
.QPLLCLK_IN (gt0_qpllclk_i),
|
||||
.QPLLREFCLK_IN (gt0_qpllrefclk_i),
|
||||
//-------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
|
||||
.DRPADDR_IN (GT0_DRPADDR_IN),
|
||||
.DRPCLK_IN (GT0_DRPCLK_IN),
|
||||
.DRPDI_IN (GT0_DRPDI_IN),
|
||||
.DRPDO_OUT (GT0_DRPDO_OUT),
|
||||
.DRPEN_IN (GT0_DRPEN_IN),
|
||||
.DRPRDY_OUT (GT0_DRPRDY_OUT),
|
||||
.DRPWE_IN (GT0_DRPWE_IN),
|
||||
//----------------------------- Eye Scan Ports -----------------------------
|
||||
.EYESCANDATAERROR_OUT (GT0_EYESCANDATAERROR_OUT),
|
||||
//---------------------- Loopback and Powerdown Ports ----------------------
|
||||
.LOOPBACK_IN (GT0_LOOPBACK_IN),
|
||||
//----------------------------- Receive Ports ------------------------------
|
||||
.RXUSERRDY_IN (GT0_RXUSERRDY_IN),
|
||||
//------------ Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
|
||||
.RXDATAVALID_OUT (GT0_RXDATAVALID_OUT),
|
||||
.RXGEARBOXSLIP_IN (GT0_RXGEARBOXSLIP_IN),
|
||||
.RXHEADER_OUT (GT0_RXHEADER_OUT),
|
||||
.RXHEADERVALID_OUT (GT0_RXHEADERVALID_OUT),
|
||||
//--------------------- Receive Ports - PRBS Detection ---------------------
|
||||
.RXPRBSCNTRESET_IN (GT0_RXPRBSCNTRESET_IN),
|
||||
.RXPRBSERR_OUT (GT0_RXPRBSERR_OUT),
|
||||
.RXPRBSSEL_IN (GT0_RXPRBSSEL_IN),
|
||||
//----------------- Receive Ports - RX Data Path interface -----------------
|
||||
.GTRXRESET_IN (GT0_GTRXRESET_IN),
|
||||
.RXDATA_OUT (GT0_RXDATA_OUT),
|
||||
.RXOUTCLK_OUT (GT0_RXOUTCLK_OUT),
|
||||
.RXPCSRESET_IN (GT0_RXPCSRESET_IN),
|
||||
.RXUSRCLK_IN (GT0_RXUSRCLK_IN),
|
||||
.RXUSRCLK2_IN (GT0_RXUSRCLK2_IN),
|
||||
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
||||
.GTXRXN_IN (GT0_GTXRXN_IN),
|
||||
.GTXRXP_IN (GT0_GTXRXP_IN),
|
||||
.RXCDRLOCK_OUT (GT0_RXCDRLOCK_OUT),
|
||||
.RXELECIDLE_OUT (GT0_RXELECIDLE_OUT),
|
||||
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
|
||||
.RXBUFRESET_IN (GT0_RXBUFRESET_IN),
|
||||
.RXBUFSTATUS_OUT (GT0_RXBUFSTATUS_OUT),
|
||||
//---------------------- Receive Ports - RX Equalizer ----------------------
|
||||
.RXLPMEN_IN (GT0_RXLPMEN_IN),
|
||||
//---------------------- Receive Ports - RX PLL Ports ----------------------
|
||||
.RXRESETDONE_OUT (GT0_RXRESETDONE_OUT),
|
||||
//----------------------------- Transmit Ports -----------------------------
|
||||
.TXUSERRDY_IN (GT0_TXUSERRDY_IN),
|
||||
//------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
|
||||
.TXHEADER_IN (GT0_TXHEADER_IN),
|
||||
.TXSEQUENCE_IN (GT0_TXSEQUENCE_IN),
|
||||
//---------------- Transmit Ports - TX Data Path interface -----------------
|
||||
.GTTXRESET_IN (GT0_GTTXRESET_IN),
|
||||
.TXDATA_IN (GT0_TXDATA_IN),
|
||||
.TXOUTCLK_OUT (GT0_TXOUTCLK_OUT),
|
||||
.TXOUTCLKFABRIC_OUT (GT0_TXOUTCLKFABRIC_OUT),
|
||||
.TXOUTCLKPCS_OUT (GT0_TXOUTCLKPCS_OUT),
|
||||
.TXPCSRESET_IN (GT0_TXPCSRESET_IN),
|
||||
.TXUSRCLK_IN (GT0_TXUSRCLK_IN),
|
||||
.TXUSRCLK2_IN (GT0_TXUSRCLK2_IN),
|
||||
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
|
||||
.GTXTXN_OUT (GT0_GTXTXN_OUT),
|
||||
.GTXTXP_OUT (GT0_GTXTXP_OUT),
|
||||
.TXINHIBIT_IN (GT0_TXINHIBIT_IN),
|
||||
.TXPRECURSOR_IN (GT0_TXPRECURSOR_IN),
|
||||
.TXPOSTCURSOR_IN (GT0_TXPOSTCURSOR_IN),
|
||||
.TXMAINCURSOR_IN (GT0_TXMAINCURSOR_IN),
|
||||
//--------------------- Transmit Ports - TX PLL Ports ----------------------
|
||||
.TXRESETDONE_OUT (GT0_TXRESETDONE_OUT),
|
||||
//------------------- Transmit Ports - TX PRBS Generator -------------------
|
||||
.TXPRBSSEL_IN (GT0_TXPRBSSEL_IN)
|
||||
|
||||
);
|
||||
|
||||
|
||||
//_________________________________________________________________________
|
||||
//_________________________________________________________________________
|
||||
//_________________________GTXE2_COMMON____________________________________
|
||||
|
||||
GTXE2_COMMON #
|
||||
(
|
||||
// Simulation attributes
|
||||
.SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
|
||||
.SIM_QPLLREFCLK_SEL (3'b001),
|
||||
.SIM_VERSION (SIM_VERSION),
|
||||
|
||||
|
||||
//----------------COMMON BLOCK Attributes---------------
|
||||
.BIAS_CFG (64'h0000040000001000),
|
||||
.COMMON_CFG (32'h00000000),
|
||||
.QPLL_CFG (27'h0680181),
|
||||
.QPLL_CLKOUT_CFG (4'b0000),
|
||||
.QPLL_COARSE_FREQ_OVRD (6'b010000),
|
||||
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
|
||||
.QPLL_CP (10'b0000011111),
|
||||
.QPLL_CP_MONITOR_EN (1'b0),
|
||||
.QPLL_DMONITOR_SEL (1'b0),
|
||||
.QPLL_FBDIV (QPLL_FBDIV_IN),
|
||||
.QPLL_FBDIV_MONITOR_EN (1'b0),
|
||||
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
|
||||
.QPLL_INIT_CFG (24'h000006),
|
||||
.QPLL_LOCK_CFG (16'h21E8),
|
||||
.QPLL_LPF (4'b1111),
|
||||
.QPLL_REFCLK_DIV (1)
|
||||
|
||||
)
|
||||
gtxe2_common_0_i
|
||||
(
|
||||
//----------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
|
||||
.DRPADDR (tied_to_ground_vec_i[7:0]),
|
||||
.DRPCLK (tied_to_ground_i),
|
||||
.DRPDI (tied_to_ground_vec_i[15:0]),
|
||||
.DRPDO (),
|
||||
.DRPEN (tied_to_ground_i),
|
||||
.DRPRDY (),
|
||||
.DRPWE (tied_to_ground_i),
|
||||
//-------------------- Common Block - Ref Clock Ports ---------------------
|
||||
.GTGREFCLK (tied_to_ground_i),
|
||||
.GTNORTHREFCLK0 (tied_to_ground_i),
|
||||
.GTNORTHREFCLK1 (tied_to_ground_i),
|
||||
.GTREFCLK0 (GT0_GTREFCLK0_COMMON_IN),
|
||||
.GTREFCLK1 (tied_to_ground_i),
|
||||
.GTSOUTHREFCLK0 (tied_to_ground_i),
|
||||
.GTSOUTHREFCLK1 (tied_to_ground_i),
|
||||
//----------------------- Common Block - QPLL Ports ------------------------
|
||||
.QPLLDMONITOR (),
|
||||
.QPLLFBCLKLOST (),
|
||||
.QPLLLOCK (GT0_QPLLLOCK_OUT),
|
||||
.QPLLLOCKDETCLK (GT0_QPLLLOCKDETCLK_IN),
|
||||
.QPLLLOCKEN (tied_to_vcc_i),
|
||||
.QPLLOUTCLK (gt0_qplloutclk_i),
|
||||
.QPLLOUTREFCLK (gt0_qplloutrefclk_i),
|
||||
.QPLLOUTRESET (tied_to_ground_i),
|
||||
.QPLLPD (tied_to_ground_i),
|
||||
.QPLLREFCLKLOST (GT0_QPLLREFCLKLOST_OUT),
|
||||
.QPLLREFCLKSEL (3'b001),
|
||||
.QPLLRESET (GT0_QPLLRESET_IN),
|
||||
.QPLLRSVD1 (16'b0000000000000000),
|
||||
.QPLLRSVD2 (5'b11111),
|
||||
.REFCLKOUTMONITOR (),
|
||||
//--------------------------- Common Block Ports ---------------------------
|
||||
.BGBYPASSB (tied_to_vcc_i),
|
||||
.BGMONITORENB (tied_to_vcc_i),
|
||||
.BGPDB (tied_to_vcc_i),
|
||||
.BGRCALOVRD (5'b00000),
|
||||
.PMARSVD (8'b00000000),
|
||||
.RCALENB (tied_to_vcc_i)
|
||||
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,732 @@
|
||||
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
|
||||
//***************************** Entity Declaration ****************************
|
||||
|
||||
module ten_gig_eth_pcs_pma_gtwizard_10gbaser_GT #
|
||||
(
|
||||
// Simulation attributes
|
||||
parameter GT_SIM_GTRESET_SPEEDUP = "false", // Set to 1 to speed up sim reset;
|
||||
parameter RX_DFE_KL_CFG2_IN = 32'h3008E56A,
|
||||
parameter PMA_RSV_IN = 32'h00000000,
|
||||
parameter PCS_RSVD_ATTR_IN = 48'h000000000000,
|
||||
parameter SIM_VERSION = ("4.0")
|
||||
)
|
||||
(
|
||||
//-------------------------------- Channel ---------------------------------
|
||||
input QPLLCLK_IN,
|
||||
input QPLLREFCLK_IN,
|
||||
//-------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
|
||||
input [8:0] DRPADDR_IN,
|
||||
input DRPCLK_IN,
|
||||
input [15:0] DRPDI_IN,
|
||||
output [15:0] DRPDO_OUT,
|
||||
input DRPEN_IN,
|
||||
output DRPRDY_OUT,
|
||||
input DRPWE_IN,
|
||||
//----------------------------- Eye Scan Ports -----------------------------
|
||||
output EYESCANDATAERROR_OUT,
|
||||
//---------------------- Loopback and Powerdown Ports ----------------------
|
||||
input [2:0] LOOPBACK_IN,
|
||||
//----------------------------- Receive Ports ------------------------------
|
||||
input RXUSERRDY_IN,
|
||||
//------------ Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
|
||||
output RXDATAVALID_OUT,
|
||||
input RXGEARBOXSLIP_IN,
|
||||
output [1:0] RXHEADER_OUT,
|
||||
output RXHEADERVALID_OUT,
|
||||
//--------------------- Receive Ports - PRBS Detection ---------------------
|
||||
input RXPRBSCNTRESET_IN,
|
||||
output RXPRBSERR_OUT,
|
||||
input [2:0] RXPRBSSEL_IN,
|
||||
//----------------- Receive Ports - RX Data Path interface -----------------
|
||||
input GTRXRESET_IN,
|
||||
output [31:0] RXDATA_OUT,
|
||||
output RXOUTCLK_OUT,
|
||||
input RXPCSRESET_IN,
|
||||
input RXUSRCLK_IN,
|
||||
input RXUSRCLK2_IN,
|
||||
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
||||
input GTXRXN_IN,
|
||||
input GTXRXP_IN,
|
||||
output RXCDRLOCK_OUT,
|
||||
output RXELECIDLE_OUT,
|
||||
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
|
||||
input RXBUFRESET_IN,
|
||||
output [2:0] RXBUFSTATUS_OUT,
|
||||
//---------------------- Receive Ports - RX Equalizer ----------------------
|
||||
input RXLPMEN_IN,
|
||||
//---------------------- Receive Ports - RX PLL Ports ----------------------
|
||||
output RXRESETDONE_OUT,
|
||||
//----------------------------- Transmit Ports -----------------------------
|
||||
input TXUSERRDY_IN,
|
||||
//------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
|
||||
input [1:0] TXHEADER_IN,
|
||||
input [6:0] TXSEQUENCE_IN,
|
||||
//---------------- Transmit Ports - TX Data Path interface -----------------
|
||||
input GTTXRESET_IN,
|
||||
input [31:0] TXDATA_IN,
|
||||
output TXOUTCLK_OUT,
|
||||
output TXOUTCLKFABRIC_OUT,
|
||||
output TXOUTCLKPCS_OUT,
|
||||
input TXPCSRESET_IN,
|
||||
input TXUSRCLK_IN,
|
||||
input TXUSRCLK2_IN,
|
||||
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
|
||||
output GTXTXN_OUT,
|
||||
output GTXTXP_OUT,
|
||||
input TXINHIBIT_IN,
|
||||
input [4:0] TXPRECURSOR_IN,
|
||||
input [4:0] TXPOSTCURSOR_IN,
|
||||
input [6:0] TXMAINCURSOR_IN,
|
||||
//--------------------- Transmit Ports - TX PLL Ports ----------------------
|
||||
output TXRESETDONE_OUT,
|
||||
//------------------- Transmit Ports - TX PRBS Generator -------------------
|
||||
input [2:0] TXPRBSSEL_IN
|
||||
|
||||
|
||||
);
|
||||
|
||||
|
||||
//***************************** Wire Declarations *****************************
|
||||
|
||||
// ground and vcc signals
|
||||
wire tied_to_ground_i;
|
||||
wire [63:0] tied_to_ground_vec_i;
|
||||
wire tied_to_vcc_i;
|
||||
wire [63:0] tied_to_vcc_vec_i;
|
||||
|
||||
|
||||
//RX Datapath signals
|
||||
wire [63:0] rxdata_i;
|
||||
wire [5:0] rxchariscomma_float_i;
|
||||
wire [5:0] rxcharisk_float_i;
|
||||
wire [5:0] rxdisperr_float_i;
|
||||
wire [5:0] rxnotintable_float_i;
|
||||
wire [5:0] rxrundisp_float_i;
|
||||
|
||||
|
||||
//TX Datapath signals
|
||||
wire [63:0] txdata_i;
|
||||
wire [5:0] txkerr_float_i;
|
||||
wire [5:0] txrundisp_float_i;
|
||||
|
||||
//
|
||||
//********************************* Main Body of Code**************************
|
||||
|
||||
//------------------------- Static signal Assigments ---------------------
|
||||
|
||||
assign tied_to_ground_i = 1'b0;
|
||||
assign tied_to_ground_vec_i = 64'h0000000000000000;
|
||||
assign tied_to_vcc_i = 1'b1;
|
||||
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
|
||||
|
||||
//------------------- GT Datapath byte mapping -----------------
|
||||
|
||||
//The GT deserializes the rightmost parallel bit (LSb) first
|
||||
assign RXDATA_OUT = rxdata_i[31:0];
|
||||
|
||||
//The GT serializes the rightmost parallel bit (LSb) first
|
||||
assign txdata_i = {tied_to_ground_vec_i[31:0], TXDATA_IN};
|
||||
|
||||
|
||||
|
||||
|
||||
//------------------------- GT Instantiations --------------------------
|
||||
GTXE2_CHANNEL #
|
||||
(
|
||||
//_______________________ Simulation-Only Attributes __________________
|
||||
|
||||
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
|
||||
.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
|
||||
.SIM_RESET_SPEEDUP (GT_SIM_GTRESET_SPEEDUP),
|
||||
.SIM_CPLLREFCLK_SEL (3'b001),
|
||||
.SIM_VERSION (SIM_VERSION),
|
||||
|
||||
|
||||
//----------------RX Byte and Word Alignment Attributes---------------
|
||||
.ALIGN_COMMA_DOUBLE ("FALSE"),
|
||||
.ALIGN_COMMA_ENABLE (10'b1111111111),
|
||||
.ALIGN_COMMA_WORD (1),
|
||||
.ALIGN_MCOMMA_DET ("FALSE"),
|
||||
.ALIGN_MCOMMA_VALUE (10'b1010000011),
|
||||
.ALIGN_PCOMMA_DET ("FALSE"),
|
||||
.ALIGN_PCOMMA_VALUE (10'b0101111100),
|
||||
.SHOW_REALIGN_COMMA ("TRUE"),
|
||||
.RXSLIDE_AUTO_WAIT (7),
|
||||
.RXSLIDE_MODE ("OFF"),
|
||||
.RX_SIG_VALID_DLY (10),
|
||||
|
||||
//----------------RX 8B/10B Decoder Attributes---------------
|
||||
.RX_DISPERR_SEQ_MATCH ("TRUE"),
|
||||
.DEC_MCOMMA_DETECT ("FALSE"),
|
||||
.DEC_PCOMMA_DETECT ("FALSE"),
|
||||
.DEC_VALID_COMMA_ONLY ("FALSE"),
|
||||
|
||||
//----------------------RX Clock Correction Attributes----------------------
|
||||
.CBCC_DATA_SOURCE_SEL ("DECODED"),
|
||||
.CLK_COR_SEQ_2_USE ("FALSE"),
|
||||
.CLK_COR_KEEP_IDLE ("FALSE"),
|
||||
.CLK_COR_MAX_LAT (19),
|
||||
.CLK_COR_MIN_LAT (15),
|
||||
.CLK_COR_PRECEDENCE ("TRUE"),
|
||||
.CLK_COR_REPEAT_WAIT (0),
|
||||
.CLK_COR_SEQ_LEN (1),
|
||||
.CLK_COR_SEQ_1_ENABLE (4'b1111),
|
||||
.CLK_COR_SEQ_1_1 (10'b0000000000),
|
||||
.CLK_COR_SEQ_1_2 (10'b0000000000),
|
||||
.CLK_COR_SEQ_1_3 (10'b0000000000),
|
||||
.CLK_COR_SEQ_1_4 (10'b0000000000),
|
||||
.CLK_CORRECT_USE ("FALSE"),
|
||||
.CLK_COR_SEQ_2_ENABLE (4'b1111),
|
||||
.CLK_COR_SEQ_2_1 (10'b0000000000),
|
||||
.CLK_COR_SEQ_2_2 (10'b0000000000),
|
||||
.CLK_COR_SEQ_2_3 (10'b0000000000),
|
||||
.CLK_COR_SEQ_2_4 (10'b0000000000),
|
||||
|
||||
//----------------------RX Channel Bonding Attributes----------------------
|
||||
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
|
||||
.CHAN_BOND_MAX_SKEW (1),
|
||||
.CHAN_BOND_SEQ_LEN (1),
|
||||
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
|
||||
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
|
||||
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
|
||||
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
|
||||
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
|
||||
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
|
||||
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
|
||||
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
|
||||
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
|
||||
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
|
||||
.CHAN_BOND_SEQ_2_USE ("FALSE"),
|
||||
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
|
||||
.FTS_LANE_DESKEW_CFG (4'b1111),
|
||||
.FTS_LANE_DESKEW_EN ("FALSE"),
|
||||
|
||||
//-------------------------RX Margin Analysis Attributes----------------------------
|
||||
.ES_CONTROL (6'b000000),
|
||||
.ES_ERRDET_EN ("FALSE"),
|
||||
.ES_EYE_SCAN_EN ("TRUE"),
|
||||
.ES_HORZ_OFFSET (12'h000),
|
||||
.ES_PMA_CFG (10'b0000000000),
|
||||
.ES_PRESCALE (5'b00000),
|
||||
.ES_QUALIFIER (80'h00000000000000000000),
|
||||
.ES_QUAL_MASK (80'h00000000000000000000),
|
||||
.ES_SDATA_MASK (80'h00000000000000000000),
|
||||
.ES_VERT_OFFSET (9'b000000000),
|
||||
|
||||
//-----------------------FPGA RX Interface Attributes-------------------------
|
||||
.RX_DATA_WIDTH (32),
|
||||
|
||||
//-------------------------PMA Attributes----------------------------
|
||||
.OUTREFCLK_SEL_INV (2'b11),
|
||||
.PMA_RSV (PMA_RSV_IN),
|
||||
.PMA_RSV2 (16'h2050),
|
||||
.PMA_RSV3 (2'b00),
|
||||
.PMA_RSV4 (32'h00000000),
|
||||
.RX_BIAS_CFG (12'b000000000100),
|
||||
.DMONITOR_CFG (24'h000A00),
|
||||
.RX_CM_SEL (2'b11),
|
||||
.RX_CM_TRIM (3'b010),
|
||||
.RX_DEBUG_CFG (12'b000000000000),
|
||||
.RX_OS_CFG (13'b0000010000000),
|
||||
.TERM_RCAL_CFG (5'b10000),
|
||||
.TERM_RCAL_OVRD (1'b0),
|
||||
.TST_RSV (32'h00000000),
|
||||
.RX_CLK25_DIV (7),
|
||||
.TX_CLK25_DIV (7),
|
||||
.UCODEER_CLR (1'b0),
|
||||
|
||||
//-------------------------PCI Express Attributes----------------------------
|
||||
.PCS_PCIE_EN ("FALSE"),
|
||||
|
||||
//-------------------------PCS Attributes----------------------------
|
||||
.PCS_RSVD_ATTR (PCS_RSVD_ATTR_IN),
|
||||
|
||||
//-----------RX Buffer Attributes------------
|
||||
.RXBUF_ADDR_MODE ("FAST"),
|
||||
.RXBUF_EIDLE_HI_CNT (4'b1000),
|
||||
.RXBUF_EIDLE_LO_CNT (4'b0000),
|
||||
.RXBUF_EN ("TRUE"),
|
||||
.RX_BUFFER_CFG (6'b000000),
|
||||
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
|
||||
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
|
||||
.RXBUF_RESET_ON_EIDLE ("FALSE"),
|
||||
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
|
||||
.RXBUFRESET_TIME (5'b00001),
|
||||
.RXBUF_THRESH_OVFLW (61),
|
||||
.RXBUF_THRESH_OVRD ("FALSE"),
|
||||
.RXBUF_THRESH_UNDFLW (4),
|
||||
.RXDLY_CFG (16'h001F),
|
||||
.RXDLY_LCFG (9'h030),
|
||||
.RXDLY_TAP_CFG (16'h0000),
|
||||
.RXPH_CFG (24'h000000),
|
||||
.RXPHDLY_CFG (24'h084020),
|
||||
.RXPH_MONITOR_SEL (5'b00000),
|
||||
.RX_XCLK_SEL ("RXREC"),
|
||||
.RX_DDI_SEL (6'b000000),
|
||||
.RX_DEFER_RESET_BUF_EN ("TRUE"),
|
||||
|
||||
//---------------------CDR Attributes-------------------------
|
||||
.RXCDR_CFG (72'h0b000023ff10400020),
|
||||
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
|
||||
.RXCDR_HOLD_DURING_EIDLE (1'b0),
|
||||
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
|
||||
.RXCDR_LOCK_CFG (6'b010101),
|
||||
|
||||
//-----------------RX Initialization and Reset Attributes-------------------
|
||||
.RXCDRFREQRESET_TIME (5'b00001),
|
||||
.RXCDRPHRESET_TIME (5'b00001),
|
||||
.RXISCANRESET_TIME (5'b00001),
|
||||
.RXPCSRESET_TIME (5'b00001),
|
||||
.RXPMARESET_TIME (5'b00011),
|
||||
|
||||
//-----------------RX OOB Signaling Attributes-------------------
|
||||
.RXOOB_CFG (7'b0000110),
|
||||
|
||||
//-----------------------RX Gearbox Attributes---------------------------
|
||||
.RXGEARBOX_EN ("TRUE"),
|
||||
.GEARBOX_MODE (3'b001),
|
||||
|
||||
//-----------------------PRBS Detection Attribute-----------------------
|
||||
.RXPRBS_ERR_LOOPBACK (1'b0),
|
||||
|
||||
//-----------Power-Down Attributes----------
|
||||
.PD_TRANS_TIME_FROM_P2 (12'h03c),
|
||||
.PD_TRANS_TIME_NONE_P2 (8'h19),
|
||||
.PD_TRANS_TIME_TO_P2 (8'h64),
|
||||
|
||||
//-----------RX OOB Signaling Attributes----------
|
||||
.SAS_MAX_COM (64),
|
||||
.SAS_MIN_COM (36),
|
||||
.SATA_BURST_SEQ_LEN (4'b1111),
|
||||
.SATA_BURST_VAL (3'b100),
|
||||
.SATA_EIDLE_VAL (3'b100),
|
||||
.SATA_MAX_BURST (8),
|
||||
.SATA_MAX_INIT (21),
|
||||
.SATA_MAX_WAKE (7),
|
||||
.SATA_MIN_BURST (4),
|
||||
.SATA_MIN_INIT (12),
|
||||
.SATA_MIN_WAKE (4),
|
||||
|
||||
//-----------RX Fabric Clock Output Control Attributes----------
|
||||
.TRANS_TIME_RATE (8'h0E),
|
||||
|
||||
//------------TX Buffer Attributes----------------
|
||||
.TXBUF_EN ("TRUE"),
|
||||
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
|
||||
.TXDLY_CFG (16'h001F),
|
||||
.TXDLY_LCFG (9'h030),
|
||||
.TXDLY_TAP_CFG (16'h0000),
|
||||
.TXPH_CFG (16'h0780),
|
||||
.TXPHDLY_CFG (24'h084020),
|
||||
.TXPH_MONITOR_SEL (5'b00000),
|
||||
.TX_XCLK_SEL ("TXOUT"),
|
||||
|
||||
//-----------------------FPGA TX Interface Attributes-------------------------
|
||||
.TX_DATA_WIDTH (32),
|
||||
|
||||
//-----------------------TX Configurable Driver Attributes-------------------------
|
||||
.TX_DEEMPH0 (5'b00000),
|
||||
.TX_DEEMPH1 (5'b00000),
|
||||
.TX_EIDLE_ASSERT_DELAY (3'b110),
|
||||
.TX_EIDLE_DEASSERT_DELAY (3'b100),
|
||||
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
|
||||
.TX_MAINCURSOR_SEL (1'b0),
|
||||
.TX_DRIVE_MODE ("DIRECT"),
|
||||
.TX_MARGIN_FULL_0 (7'b1001110),
|
||||
.TX_MARGIN_FULL_1 (7'b1001001),
|
||||
.TX_MARGIN_FULL_2 (7'b1000101),
|
||||
.TX_MARGIN_FULL_3 (7'b1000010),
|
||||
.TX_MARGIN_FULL_4 (7'b1000000),
|
||||
.TX_MARGIN_LOW_0 (7'b1000110),
|
||||
.TX_MARGIN_LOW_1 (7'b1000100),
|
||||
.TX_MARGIN_LOW_2 (7'b1000010),
|
||||
.TX_MARGIN_LOW_3 (7'b1000000),
|
||||
.TX_MARGIN_LOW_4 (7'b1000000),
|
||||
|
||||
//-----------------------TX Gearbox Attributes--------------------------
|
||||
.TXGEARBOX_EN ("TRUE"),
|
||||
|
||||
//-----------------------TX Initialization and Reset Attributes--------------------------
|
||||
.TXPCSRESET_TIME (5'b00001),
|
||||
.TXPMARESET_TIME (5'b00001),
|
||||
|
||||
//-----------------------TX Receiver Detection Attributes--------------------------
|
||||
.TX_RXDETECT_CFG (14'h1832),
|
||||
.TX_RXDETECT_REF (3'b100),
|
||||
|
||||
//--------------------------CPLL Attributes----------------------------
|
||||
.CPLL_CFG (24'hBC07DC),
|
||||
.CPLL_FBDIV (4),
|
||||
.CPLL_FBDIV_45 (5),
|
||||
.CPLL_INIT_CFG (24'h00001E),
|
||||
.CPLL_LOCK_CFG (16'h01E8),
|
||||
.CPLL_REFCLK_DIV (1),
|
||||
.RXOUT_DIV (1),
|
||||
.TXOUT_DIV (1),
|
||||
.SATA_CPLL_CFG ("VCO_3000MHZ"),
|
||||
|
||||
//------------RX Initialization and Reset Attributes-------------
|
||||
.RXDFELPMRESET_TIME (7'b0001111),
|
||||
|
||||
//------------RX Equalizer Attributes-------------
|
||||
.RXLPM_HF_CFG (14'b00000011110000),
|
||||
.RXLPM_LF_CFG (14'b00000011110000),
|
||||
.RX_DFE_GAIN_CFG (23'h020FEA),
|
||||
.RX_DFE_H2_CFG (12'b000000000000),
|
||||
.RX_DFE_H3_CFG (12'b000001000000),
|
||||
.RX_DFE_H4_CFG (11'b00011110000),
|
||||
.RX_DFE_H5_CFG (11'b00011100000),
|
||||
.RX_DFE_KL_CFG (13'b0000011111110),
|
||||
.RX_DFE_LPM_CFG (16'h0954),
|
||||
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
|
||||
.RX_DFE_UT_CFG (17'b10001111000000000),
|
||||
.RX_DFE_VP_CFG (17'b00011111100000011),
|
||||
|
||||
//-----------------------Power-Down Attributes-------------------------
|
||||
.RX_CLKMUX_PD (1'b1),
|
||||
.TX_CLKMUX_PD (1'b1),
|
||||
|
||||
//-----------------------FPGA RX Interface Attribute-------------------------
|
||||
.RX_INT_DATAWIDTH (1),
|
||||
|
||||
//-----------------------FPGA TX Interface Attribute-------------------------
|
||||
.TX_INT_DATAWIDTH (1),
|
||||
|
||||
//----------------TX Configurable Driver Attributes---------------
|
||||
.TX_QPI_STATUS_EN (1'b0),
|
||||
|
||||
//-----------------------RX Equalizer Attributes--------------------------
|
||||
.RX_DFE_KL_CFG2 (RX_DFE_KL_CFG2_IN),
|
||||
.RX_DFE_XYD_CFG (13'b0000000000000),
|
||||
|
||||
//-----------------------TX Configurable Driver Attributes--------------------------
|
||||
.TX_PREDRIVER_MODE (1'b0)
|
||||
|
||||
|
||||
)
|
||||
gtxe2_i
|
||||
(
|
||||
|
||||
//-------------------------------- Channel ---------------------------------
|
||||
.CFGRESET (tied_to_ground_i),
|
||||
.CLKRSVD (4'b0000),
|
||||
.DMONITOROUT (),
|
||||
.GTRESETSEL (tied_to_ground_i),
|
||||
.GTRSVD (16'b0000000000000000),
|
||||
.QPLLCLK (QPLLCLK_IN),
|
||||
.QPLLREFCLK (QPLLREFCLK_IN),
|
||||
.RESETOVRD (tied_to_ground_i),
|
||||
//-------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
|
||||
.DRPADDR (DRPADDR_IN),
|
||||
.DRPCLK (DRPCLK_IN),
|
||||
.DRPDI (DRPDI_IN),
|
||||
.DRPDO (DRPDO_OUT),
|
||||
.DRPEN (DRPEN_IN),
|
||||
.DRPRDY (DRPRDY_OUT),
|
||||
.DRPWE (DRPWE_IN),
|
||||
//----------------------- Channel - Ref Clock Ports ------------------------
|
||||
.GTGREFCLK (tied_to_ground_i),
|
||||
.GTNORTHREFCLK0 (tied_to_ground_i),
|
||||
.GTNORTHREFCLK1 (tied_to_ground_i),
|
||||
.GTREFCLK0 (tied_to_ground_i),
|
||||
.GTREFCLK1 (tied_to_ground_i),
|
||||
.GTREFCLKMONITOR (),
|
||||
.GTSOUTHREFCLK0 (tied_to_ground_i),
|
||||
.GTSOUTHREFCLK1 (tied_to_ground_i),
|
||||
//------------------------------ Channel PLL -------------------------------
|
||||
.CPLLFBCLKLOST (),
|
||||
.CPLLLOCK (),
|
||||
.CPLLLOCKDETCLK (tied_to_ground_i),
|
||||
.CPLLLOCKEN (tied_to_vcc_i),
|
||||
.CPLLPD (tied_to_vcc_i),
|
||||
.CPLLREFCLKLOST (),
|
||||
.CPLLREFCLKSEL (3'b001),
|
||||
.CPLLRESET (tied_to_ground_i),
|
||||
//----------------------------- Eye Scan Ports -----------------------------
|
||||
.EYESCANDATAERROR (EYESCANDATAERROR_OUT),
|
||||
.EYESCANMODE (tied_to_ground_i),
|
||||
.EYESCANRESET (tied_to_ground_i),
|
||||
.EYESCANTRIGGER (tied_to_ground_i),
|
||||
//---------------------- Loopback and Powerdown Ports ----------------------
|
||||
.LOOPBACK (LOOPBACK_IN),
|
||||
.RXPD (2'b00),
|
||||
.TXPD (2'b00),
|
||||
//--------------------------- PCS Reserved Ports ---------------------------
|
||||
.PCSRSVDIN (16'b0000000000000000),
|
||||
.PCSRSVDIN2 (5'b00000),
|
||||
.PCSRSVDOUT (),
|
||||
//--------------------------- PMA Reserved Ports ---------------------------
|
||||
.PMARSVDIN (5'b00000),
|
||||
.PMARSVDIN2 (5'b00000),
|
||||
//----------------------------- Receive Ports ------------------------------
|
||||
.RXQPIEN (tied_to_ground_i),
|
||||
.RXQPISENN (),
|
||||
.RXQPISENP (),
|
||||
.RXSYSCLKSEL (2'b11),
|
||||
.RXUSERRDY (RXUSERRDY_IN),
|
||||
//------------ Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
|
||||
.RXDATAVALID (RXDATAVALID_OUT),
|
||||
.RXGEARBOXSLIP (RXGEARBOXSLIP_IN),
|
||||
.RXHEADER ({rxheader_float_i,RXHEADER_OUT}),
|
||||
.RXHEADERVALID (RXHEADERVALID_OUT),
|
||||
.RXSTARTOFSEQ (),
|
||||
//--------------------- Receive Ports - 8b10b Decoder ----------------------
|
||||
.RX8B10BEN (tied_to_ground_i),
|
||||
.RXCHARISCOMMA (),
|
||||
.RXCHARISK (),
|
||||
.RXDISPERR (),
|
||||
.RXNOTINTABLE (),
|
||||
//----------------- Receive Ports - Channel Bonding Ports ------------------
|
||||
.RXCHANBONDSEQ (),
|
||||
.RXCHBONDEN (tied_to_ground_i),
|
||||
.RXCHBONDI (5'b00000),
|
||||
.RXCHBONDLEVEL (tied_to_ground_vec_i[2:0]),
|
||||
.RXCHBONDMASTER (tied_to_ground_i),
|
||||
.RXCHBONDO (),
|
||||
.RXCHBONDSLAVE (tied_to_ground_i),
|
||||
//----------------- Receive Ports - Channel Bonding Ports -----------------
|
||||
.RXCHANISALIGNED (),
|
||||
.RXCHANREALIGN (),
|
||||
//----------------- Receive Ports - Clock Correction Ports -----------------
|
||||
.RXCLKCORCNT (),
|
||||
//------------- Receive Ports - Comma Detection and Alignment --------------
|
||||
.RXBYTEISALIGNED (),
|
||||
.RXBYTEREALIGN (),
|
||||
.RXCOMMADET (),
|
||||
.RXCOMMADETEN (tied_to_ground_i),
|
||||
.RXMCOMMAALIGNEN (tied_to_ground_i),
|
||||
.RXPCOMMAALIGNEN (tied_to_ground_i),
|
||||
.RXSLIDE (RXGEARBOXSLIP_IN),
|
||||
//--------------------- Receive Ports - PRBS Detection ---------------------
|
||||
.RXPRBSCNTRESET (RXPRBSCNTRESET_IN),
|
||||
.RXPRBSERR (RXPRBSERR_OUT),
|
||||
.RXPRBSSEL (RXPRBSSEL_IN),
|
||||
//----------------- Receive Ports - RX Data Path interface -----------------
|
||||
.GTRXRESET (GTRXRESET_IN),
|
||||
.RXDATA (rxdata_i),
|
||||
.RXOUTCLK (RXOUTCLK_OUT),
|
||||
.RXOUTCLKFABRIC (),
|
||||
.RXOUTCLKPCS (),
|
||||
.RXOUTCLKSEL (3'b010),
|
||||
.RXPCSRESET (RXPCSRESET_IN),
|
||||
.RXPMARESET (tied_to_ground_i),
|
||||
.RXUSRCLK (RXUSRCLK_IN),
|
||||
.RXUSRCLK2 (RXUSRCLK2_IN),
|
||||
//---------- Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
|
||||
.RXDFEAGCHOLD (tied_to_ground_i),
|
||||
.RXDFEAGCOVRDEN (tied_to_ground_i),
|
||||
.RXDFECM1EN (tied_to_ground_i),
|
||||
.RXDFELFHOLD (tied_to_ground_i),
|
||||
.RXDFELFOVRDEN (tied_to_vcc_i),
|
||||
.RXDFELPMRESET (tied_to_ground_i),
|
||||
.RXDFETAP2HOLD (tied_to_ground_i),
|
||||
.RXDFETAP2OVRDEN (tied_to_ground_i),
|
||||
.RXDFETAP3HOLD (tied_to_ground_i),
|
||||
.RXDFETAP3OVRDEN (tied_to_ground_i),
|
||||
.RXDFETAP4HOLD (tied_to_ground_i),
|
||||
.RXDFETAP4OVRDEN (tied_to_ground_i),
|
||||
.RXDFETAP5HOLD (tied_to_ground_i),
|
||||
.RXDFETAP5OVRDEN (tied_to_ground_i),
|
||||
.RXDFEUTHOLD (tied_to_ground_i),
|
||||
.RXDFEUTOVRDEN (tied_to_ground_i),
|
||||
.RXDFEVPHOLD (tied_to_ground_i),
|
||||
.RXDFEVPOVRDEN (tied_to_ground_i),
|
||||
.RXDFEVSEN (tied_to_ground_i),
|
||||
.RXDFEXYDEN (tied_to_ground_i),
|
||||
.RXDFEXYDHOLD (tied_to_ground_i),
|
||||
.RXDFEXYDOVRDEN (tied_to_ground_i),
|
||||
.RXMONITOROUT (),
|
||||
.RXMONITORSEL (2'b00),
|
||||
.RXOSHOLD (tied_to_ground_i),
|
||||
.RXOSOVRDEN (tied_to_ground_i),
|
||||
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
||||
.GTXRXN (GTXRXN_IN),
|
||||
.GTXRXP (GTXRXP_IN),
|
||||
.RXCDRFREQRESET (tied_to_ground_i),
|
||||
.RXCDRHOLD (tied_to_ground_i),
|
||||
.RXCDRLOCK (RXCDRLOCK_OUT),
|
||||
.RXCDROVRDEN (tied_to_ground_i),
|
||||
.RXCDRRESET (tied_to_ground_i),
|
||||
.RXCDRRESETRSV (tied_to_ground_i),
|
||||
.RXELECIDLE (RXELECIDLE_OUT),
|
||||
.RXELECIDLEMODE (2'b11),
|
||||
.RXLPMHFHOLD (tied_to_ground_i),
|
||||
.RXLPMHFOVRDEN (tied_to_ground_i),
|
||||
.RXLPMLFHOLD (tied_to_ground_i),
|
||||
.RXLPMLFKLOVRDEN (tied_to_ground_i),
|
||||
.RXOOBRESET (tied_to_ground_i),
|
||||
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
|
||||
.RXBUFRESET (RXBUFRESET_IN),
|
||||
.RXBUFSTATUS (RXBUFSTATUS_OUT),
|
||||
.RXDDIEN (tied_to_ground_i),
|
||||
.RXDLYBYPASS (tied_to_vcc_i),
|
||||
.RXDLYEN (tied_to_ground_i),
|
||||
.RXDLYOVRDEN (tied_to_ground_i),
|
||||
.RXDLYSRESET (tied_to_ground_i),
|
||||
.RXDLYSRESETDONE (),
|
||||
.RXPHALIGN (tied_to_ground_i),
|
||||
.RXPHALIGNDONE (),
|
||||
.RXPHALIGNEN (tied_to_ground_i),
|
||||
.RXPHDLYPD (tied_to_ground_i),
|
||||
.RXPHDLYRESET (tied_to_ground_i),
|
||||
.RXPHMONITOR (),
|
||||
.RXPHOVRDEN (tied_to_ground_i),
|
||||
.RXPHSLIPMONITOR (),
|
||||
.RXSTATUS (),
|
||||
//---------------------- Receive Ports - RX Equalizer ----------------------
|
||||
.RXLPMEN (RXLPMEN_IN),
|
||||
//---------------------- Receive Ports - RX PLL Ports ----------------------
|
||||
.RXRATE (tied_to_ground_vec_i[2:0]),
|
||||
.RXRATEDONE (),
|
||||
.RXRESETDONE (RXRESETDONE_OUT),
|
||||
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
|
||||
.PHYSTATUS (),
|
||||
.RXVALID (),
|
||||
//--------------- Receive Ports - RX Polarity Control Ports ----------------
|
||||
.RXPOLARITY (tied_to_ground_i),
|
||||
//------------------- Receive Ports - RX Ports for SATA --------------------
|
||||
.RXCOMINITDET (),
|
||||
.RXCOMSASDET (),
|
||||
.RXCOMWAKEDET (),
|
||||
//----------------------------- Transmit Ports -----------------------------
|
||||
.SETERRSTATUS (tied_to_ground_i),
|
||||
.TSTIN (20'b11111111111111111111),
|
||||
.TSTOUT (),
|
||||
.TXPHDLYTSTCLK (tied_to_ground_i),
|
||||
.TXPOSTCURSOR (TXPOSTCURSOR_IN),
|
||||
.TXPOSTCURSORINV (tied_to_ground_i),
|
||||
.TXPRECURSOR (TXPRECURSOR_IN),
|
||||
.TXPRECURSORINV (tied_to_ground_i),
|
||||
.TXQPIBIASEN (tied_to_ground_i),
|
||||
.TXQPISENN (),
|
||||
.TXQPISENP (),
|
||||
.TXQPISTRONGPDOWN (tied_to_ground_i),
|
||||
.TXQPIWEAKPUP (tied_to_ground_i),
|
||||
.TXSYSCLKSEL (2'b11),
|
||||
.TXUSERRDY (TXUSERRDY_IN),
|
||||
//------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
|
||||
.TXGEARBOXREADY (),
|
||||
.TXHEADER ({tied_to_ground_i,TXHEADER_IN}),
|
||||
.TXSEQUENCE (TXSEQUENCE_IN),
|
||||
.TXSTARTSEQ (tied_to_ground_i),
|
||||
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
|
||||
.TX8B10BBYPASS (tied_to_ground_vec_i[7:0]),
|
||||
.TX8B10BEN (tied_to_ground_i),
|
||||
.TXCHARDISPMODE (tied_to_ground_vec_i[7:0]),
|
||||
.TXCHARDISPVAL (tied_to_ground_vec_i[7:0]),
|
||||
.TXCHARISK (tied_to_ground_vec_i[7:0]),
|
||||
//---------- Transmit Ports - TX Buffer and Phase Alignment Ports ----------
|
||||
.TXBUFSTATUS (),
|
||||
.TXDLYBYPASS (tied_to_vcc_i),
|
||||
.TXDLYEN (tied_to_ground_i),
|
||||
.TXDLYHOLD (tied_to_ground_i),
|
||||
.TXDLYOVRDEN (tied_to_ground_i),
|
||||
.TXDLYSRESET (tied_to_ground_i),
|
||||
.TXDLYSRESETDONE (),
|
||||
.TXDLYUPDOWN (tied_to_ground_i),
|
||||
.TXPHALIGN (tied_to_ground_i),
|
||||
.TXPHALIGNDONE (),
|
||||
.TXPHALIGNEN (tied_to_ground_i),
|
||||
.TXPHDLYPD (tied_to_ground_i),
|
||||
.TXPHDLYRESET (tied_to_ground_i),
|
||||
.TXPHINIT (tied_to_ground_i),
|
||||
.TXPHINITDONE (),
|
||||
.TXPHOVRDEN (tied_to_ground_i),
|
||||
//---------------- Transmit Ports - TX Data Path interface -----------------
|
||||
.GTTXRESET (GTTXRESET_IN),
|
||||
.TXDATA (txdata_i),
|
||||
.TXOUTCLK (TXOUTCLK_OUT),
|
||||
.TXOUTCLKFABRIC (TXOUTCLKFABRIC_OUT),
|
||||
.TXOUTCLKPCS (TXOUTCLKPCS_OUT),
|
||||
.TXOUTCLKSEL (3'b010),
|
||||
.TXPCSRESET (TXPCSRESET_IN),
|
||||
.TXPMARESET (tied_to_ground_i),
|
||||
.TXUSRCLK (TXUSRCLK_IN),
|
||||
.TXUSRCLK2 (TXUSRCLK2_IN),
|
||||
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
|
||||
.GTXTXN (GTXTXN_OUT),
|
||||
.GTXTXP (GTXTXP_OUT),
|
||||
.TXBUFDIFFCTRL (3'b100),
|
||||
.TXDIFFCTRL (4'b1110),
|
||||
.TXDIFFPD (tied_to_ground_i),
|
||||
.TXINHIBIT (TXINHIBIT_IN),
|
||||
.TXMAINCURSOR (TXMAINCURSOR_IN),
|
||||
.TXPDELECIDLEMODE (tied_to_ground_i),
|
||||
.TXPISOPD (tied_to_ground_i),
|
||||
//--------------------- Transmit Ports - TX PLL Ports ----------------------
|
||||
.TXRATE (tied_to_ground_vec_i[2:0]),
|
||||
.TXRATEDONE (),
|
||||
.TXRESETDONE (TXRESETDONE_OUT),
|
||||
//------------------- Transmit Ports - TX PRBS Generator -------------------
|
||||
.TXPRBSFORCEERR (tied_to_ground_i),
|
||||
.TXPRBSSEL (TXPRBSSEL_IN),
|
||||
//------------------ Transmit Ports - TX Polarity Control ------------------
|
||||
.TXPOLARITY (tied_to_ground_i),
|
||||
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
|
||||
.TXDEEMPH (tied_to_ground_i),
|
||||
.TXDETECTRX (tied_to_ground_i),
|
||||
.TXELECIDLE (tied_to_ground_i),
|
||||
.TXMARGIN (tied_to_ground_vec_i[2:0]),
|
||||
.TXSWING (tied_to_ground_i),
|
||||
//------------------- Transmit Ports - TX Ports for SATA -------------------
|
||||
.TXCOMFINISH (),
|
||||
.TXCOMINIT (tied_to_ground_i),
|
||||
.TXCOMSAS (tied_to_ground_i),
|
||||
.TXCOMWAKE (tied_to_ground_i)
|
||||
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
+970
@@ -0,0 +1,970 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// Title : Block level wrapper
|
||||
// Project : 10GBASE-R
|
||||
//-----------------------------------------------------------------------------
|
||||
// File : ten_gig_eth_pcs_pma_block.v
|
||||
//-----------------------------------------------------------------------------
|
||||
// Description: This file is a wrapper for the 10GBASE-R core. It contains the
|
||||
// 10GBASE-R core, the transceivers and some transceiver logic.
|
||||
//-----------------------------------------------------------------------------
|
||||
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
module ten_gig_eth_pcs_pma_block #
|
||||
(
|
||||
parameter EXAMPLE_SIM_GTRESET_SPEEDUP = "FALSE"
|
||||
)
|
||||
(
|
||||
// input refclk_n,
|
||||
// input refclk_p,
|
||||
input refclk156,
|
||||
input refclk156_buf,
|
||||
output clk156,
|
||||
output txclk322,
|
||||
output rxclk322,
|
||||
output dclk,
|
||||
input areset,
|
||||
input reset,
|
||||
input txreset322,
|
||||
input rxreset322,
|
||||
input dclk_reset,
|
||||
output txp,
|
||||
output txn,
|
||||
input rxp,
|
||||
input rxn,
|
||||
input [63:0] xgmii_txd,
|
||||
input [7:0] xgmii_txc,
|
||||
output [63:0] xgmii_rxd,
|
||||
output [7:0] xgmii_rxc,
|
||||
input mdc,
|
||||
input mdio_in,
|
||||
output mdio_out,
|
||||
output mdio_tri,
|
||||
input [4 : 0] prtad,
|
||||
output [7 : 0] core_status,
|
||||
output tx_resetdone,
|
||||
output rx_resetdone,
|
||||
input signal_detect,
|
||||
input tx_fault,
|
||||
output tx_disable);
|
||||
|
||||
// Static signal Assigments
|
||||
wire tied_to_ground_i;
|
||||
wire [63:0] tied_to_ground_vec_i;
|
||||
wire tied_to_vcc_i;
|
||||
wire [7:0] tied_to_vcc_vec_i;
|
||||
assign tied_to_ground_i = 1'b0;
|
||||
assign tied_to_ground_vec_i = 64'h0000000000000000;
|
||||
assign tied_to_vcc_i = 1'b1;
|
||||
assign tied_to_vcc_vec_i = 8'hff;
|
||||
|
||||
|
||||
wire [31:0] gt_txd;
|
||||
wire [7:0] gt_txc;
|
||||
|
||||
wire [31:0] gt_rxd;
|
||||
wire [7:0] gt_rxc;
|
||||
|
||||
reg [31:0] gt_rxd_d1;
|
||||
reg [7:0] gt_rxc_d1;
|
||||
|
||||
wire [15:0] gt0_drpdi_i;
|
||||
wire [15:0] gt0_drpaddr_i;
|
||||
wire [15:0] gt0_drpdo_i;
|
||||
|
||||
wire gt0_rxgearboxslip_i;
|
||||
wire drp_gnt;
|
||||
wire drp_req;
|
||||
|
||||
wire [2:0] gt0_loopback_i;
|
||||
wire gt0_clear_rx_prbs_err_count_i;
|
||||
|
||||
wire gt0_qplllock_i;
|
||||
wire gt0_rxusrclk_i;
|
||||
wire gt0_txusrclk_i;
|
||||
wire gt0_gtrxreset_i;
|
||||
wire gt0_gttxreset_i;
|
||||
|
||||
reg pma_resetout_reg;
|
||||
wire pma_resetout_rising;
|
||||
reg pcs_resetout_reg;
|
||||
wire pcs_resetout_rising;
|
||||
|
||||
wire pma_resetout;
|
||||
wire pcs_resetout;
|
||||
|
||||
wire clk156_buf;
|
||||
wire dclk_buf;
|
||||
|
||||
wire gt0_rxuserrdy_i;
|
||||
wire gt0_txuserrdy_i;
|
||||
reg gt0_rxuserrdy_r = 1'b0;
|
||||
reg gt0_txuserrdy_r = 1'b0;
|
||||
wire GTTXRESET_IN;
|
||||
wire GTRXRESET_IN;
|
||||
wire QPLLRESET_IN;
|
||||
reg [7:0] reset_counter = 8'h00;
|
||||
reg [3:0] reset_pulse;
|
||||
wire mmcm_locked;
|
||||
|
||||
reg [19:0] rxuserrdy_counter = 20'h0;
|
||||
// Nominal wait time of 50000 UI = 757 cyles of 156.25MHz clock
|
||||
localparam [19:0] RXRESETTIME_NOM = 20'h002F5;
|
||||
// Maximum wait time of 37x10^6 UI = 560782 cycles of 156.25MHz clock
|
||||
localparam [19:0] RXRESETTIME_MAX = 20'h89000;
|
||||
|
||||
// Set this according to requirements
|
||||
wire [19:0] RXRESETTIME = RXRESETTIME_NOM;
|
||||
|
||||
// Aid the detection of a cable/board being pulled
|
||||
reg [3:0] rx_sample = 4'b0000; // Used to monitor RX data for a cable pull
|
||||
reg [3:0] rx_sample_prev = 4'b0000; // Used to monitor RX data for a cable pull
|
||||
reg [19:0] cable_pull_watchdog = 20'h20000; // 128K cycles
|
||||
reg [1:0] cable_pull_watchdog_event = 2'b00; // Count events which suggest no cable pull
|
||||
reg cable_pull_reset = 1'b0; // This is set when the watchdog above gets to 0.
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg cable_pull_reset_reg = 1'b0; // This is set when the watchdog above gets to 0.
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg cable_pull_reset_reg_reg = 1'b0;
|
||||
reg cable_pull_reset_rising = 1'b0;
|
||||
reg cable_pull_reset_rising_reg = 1'b0;
|
||||
|
||||
// Aid the detection of a cable/board being plugged back in
|
||||
reg cable_unpull_enable = 1'b0;
|
||||
reg [19:0] cable_unpull_watchdog = 20'h20000;
|
||||
reg [10:0] cable_unpull_watchdog_event = 11'b0;
|
||||
reg cable_unpull_reset = 1'b0;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg cable_unpull_reset_reg = 1'b0;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg cable_unpull_reset_reg_reg = 1'b0;
|
||||
reg cable_unpull_reset_rising = 1'b0;
|
||||
reg cable_unpull_reset_rising_reg = 1'b0;
|
||||
|
||||
wire signal_detect_comb;
|
||||
wire cable_is_pulled;
|
||||
|
||||
|
||||
// If no arbitration is required on the GT DRP ports then connect REQ to GNT...
|
||||
assign drp_gnt = drp_req;
|
||||
|
||||
ten_gig_eth_pcs_pma
|
||||
ten_gig_eth_pcs_pma_core (
|
||||
.reset(reset),
|
||||
.txreset322(txreset322),
|
||||
.rxreset322(rxreset322),
|
||||
.dclk_reset(dclk_reset),
|
||||
.pma_resetout(pma_resetout),
|
||||
.pcs_resetout(pcs_resetout),
|
||||
.clk156(clk156),
|
||||
.txusrclk2(txclk322),
|
||||
.rxusrclk2(rxclk322),
|
||||
.dclk(dclk),
|
||||
.xgmii_txd(xgmii_txd),
|
||||
.xgmii_txc(xgmii_txc),
|
||||
.xgmii_rxd(xgmii_rxd),
|
||||
.xgmii_rxc(xgmii_rxc),
|
||||
.mdc(mdc),
|
||||
.mdio_in(mdio_in),
|
||||
.mdio_out(mdio_out),
|
||||
.mdio_tri(mdio_tri),
|
||||
.prtad(prtad),
|
||||
.core_status(core_status),
|
||||
.pma_pmd_type(3'b101),
|
||||
.drp_req(drp_req),
|
||||
.drp_gnt(drp_gnt),
|
||||
.drp_den(gt0_drpen_i),
|
||||
.drp_dwe(gt0_drpwe_i),
|
||||
.drp_daddr(gt0_drpaddr_i),
|
||||
.drp_di(gt0_drpdi_i),
|
||||
.drp_drdy(gt0_drprdy_i),
|
||||
.drp_drpdo(gt0_drpdo_i),
|
||||
.resetdone(resetdone),
|
||||
.gt_txd(gt_txd),
|
||||
.gt_txc(gt_txc),
|
||||
.gt_rxd(gt_rxd_d1),
|
||||
.gt_rxc(gt_rxc_d1),
|
||||
.gt_slip(gt0_rxgearboxslip_i),
|
||||
.signal_detect(signal_detect_comb),
|
||||
.tx_fault(tx_fault),
|
||||
.tx_disable(tx_disable),
|
||||
.tx_prbs31_en(tx_prbs31_en),
|
||||
.rx_prbs31_en(rx_prbs31_en),
|
||||
.clear_rx_prbs_err_count(gt0_clear_rx_prbs_err_count_i),
|
||||
.loopback_ctrl(gt0_loopback_i));
|
||||
|
||||
// Make the GT Wizard output connect to the core and top level i/f
|
||||
//assign Q1_CLK0_GTREFCLK_PAD_N_IN = refclk_n;
|
||||
//assign Q1_CLK0_GTREFCLK_PAD_P_IN = refclk_p;
|
||||
|
||||
wire gt0_txusrclk2_i;
|
||||
wire gt0_rxusrclk2_i;
|
||||
wire gt0_drpclk_i;
|
||||
wire clkfbout;
|
||||
|
||||
//
|
||||
// Single ended 156MHz reference clock brought in from upper hierarchy now.
|
||||
//
|
||||
wire q1_clk0_refclk_i = refclk156;
|
||||
|
||||
wire q1_clk0_refclk_i_bufh = refclk156_buf;
|
||||
|
||||
assign txclk322 = gt0_txusrclk2_i;
|
||||
assign rxclk322 = gt0_rxusrclk2_i;
|
||||
assign gt0_drpclk_i = dclk;
|
||||
|
||||
assign RXN_IN = rxn;
|
||||
assign RXP_IN = rxp;
|
||||
|
||||
wire TXN_OUT;
|
||||
wire TXP_OUT;
|
||||
|
||||
assign txn = TXN_OUT;
|
||||
assign txp = TXP_OUT;
|
||||
|
||||
wire gt0_txresetdone_i;
|
||||
wire gt0_rxresetdone_i;
|
||||
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg gt0_txresetdone_i_rega = 1'b0;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg gt0_txresetdone_i_reg = 1'b0;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg gt0_rxresetdone_i_rega = 1'b0;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg gt0_rxresetdone_i_reg = 1'b0;
|
||||
|
||||
reg gt0_rxresetdone_i_regrx322 = 1'b0;
|
||||
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
if(mmcm_locked == 1'b1) begin
|
||||
gt0_txresetdone_i_rega <= gt0_txresetdone_i;
|
||||
gt0_txresetdone_i_reg <= gt0_txresetdone_i_rega;
|
||||
gt0_rxresetdone_i_rega <= gt0_rxresetdone_i;
|
||||
gt0_rxresetdone_i_reg <= gt0_rxresetdone_i_rega;
|
||||
end
|
||||
end
|
||||
|
||||
assign resetdone = gt0_txresetdone_i_reg && gt0_rxresetdone_i_reg;
|
||||
assign tx_resetdone = gt0_txresetdone_i_reg && mmcm_locked;
|
||||
assign rx_resetdone = gt0_rxresetdone_i_reg && mmcm_locked;
|
||||
|
||||
wire [1:0] gt0_txheader_i;
|
||||
wire [6:0] gt0_txsequence_i;
|
||||
wire [31:0] gt0_txdata_i;
|
||||
|
||||
reg gt0_rxbufreset_i = 1'b0;
|
||||
wire [2:0] gt0_rxbufstatus_i;
|
||||
|
||||
assign gt0_txdata_i[0 ] = gt_txd[31];
|
||||
assign gt0_txdata_i[1 ] = gt_txd[30];
|
||||
assign gt0_txdata_i[2 ] = gt_txd[29];
|
||||
assign gt0_txdata_i[3 ] = gt_txd[28];
|
||||
assign gt0_txdata_i[4 ] = gt_txd[27];
|
||||
assign gt0_txdata_i[5 ] = gt_txd[26];
|
||||
assign gt0_txdata_i[6 ] = gt_txd[25];
|
||||
assign gt0_txdata_i[7 ] = gt_txd[24];
|
||||
assign gt0_txdata_i[8 ] = gt_txd[23];
|
||||
assign gt0_txdata_i[9 ] = gt_txd[22];
|
||||
assign gt0_txdata_i[10] = gt_txd[21];
|
||||
assign gt0_txdata_i[11] = gt_txd[20];
|
||||
assign gt0_txdata_i[12] = gt_txd[19];
|
||||
assign gt0_txdata_i[13] = gt_txd[18];
|
||||
assign gt0_txdata_i[14] = gt_txd[17];
|
||||
assign gt0_txdata_i[15] = gt_txd[16];
|
||||
assign gt0_txdata_i[16] = gt_txd[15];
|
||||
assign gt0_txdata_i[17] = gt_txd[14];
|
||||
assign gt0_txdata_i[18] = gt_txd[13];
|
||||
assign gt0_txdata_i[19] = gt_txd[12];
|
||||
assign gt0_txdata_i[20] = gt_txd[11];
|
||||
assign gt0_txdata_i[21] = gt_txd[10];
|
||||
assign gt0_txdata_i[22] = gt_txd[9 ];
|
||||
assign gt0_txdata_i[23] = gt_txd[8 ];
|
||||
assign gt0_txdata_i[24] = gt_txd[7 ];
|
||||
assign gt0_txdata_i[25] = gt_txd[6 ];
|
||||
assign gt0_txdata_i[26] = gt_txd[5 ];
|
||||
assign gt0_txdata_i[27] = gt_txd[4 ];
|
||||
assign gt0_txdata_i[28] = gt_txd[3 ];
|
||||
assign gt0_txdata_i[29] = gt_txd[2 ];
|
||||
assign gt0_txdata_i[30] = gt_txd[1 ];
|
||||
assign gt0_txdata_i[31] = gt_txd[0 ];
|
||||
assign gt0_txheader_i[0] = gt_txc[1];
|
||||
assign gt0_txheader_i[1] = gt_txc[0];
|
||||
assign gt0_txsequence_i = {1'b0, gt_txc[7:2]};
|
||||
|
||||
wire [31:0] gt0_rxdata_i;
|
||||
wire [1:0] gt0_rxheader_i;
|
||||
wire gt0_rxheadervalid_i;
|
||||
wire gt0_rxdatavalid_i;
|
||||
|
||||
assign gt_rxd[0 ] = gt0_rxdata_i[31];
|
||||
assign gt_rxd[1 ] = gt0_rxdata_i[30];
|
||||
assign gt_rxd[2 ] = gt0_rxdata_i[29];
|
||||
assign gt_rxd[3 ] = gt0_rxdata_i[28];
|
||||
assign gt_rxd[4 ] = gt0_rxdata_i[27];
|
||||
assign gt_rxd[5 ] = gt0_rxdata_i[26];
|
||||
assign gt_rxd[6 ] = gt0_rxdata_i[25];
|
||||
assign gt_rxd[7 ] = gt0_rxdata_i[24];
|
||||
assign gt_rxd[8 ] = gt0_rxdata_i[23];
|
||||
assign gt_rxd[9 ] = gt0_rxdata_i[22];
|
||||
assign gt_rxd[10] = gt0_rxdata_i[21];
|
||||
assign gt_rxd[11] = gt0_rxdata_i[20];
|
||||
assign gt_rxd[12] = gt0_rxdata_i[19];
|
||||
assign gt_rxd[13] = gt0_rxdata_i[18];
|
||||
assign gt_rxd[14] = gt0_rxdata_i[17];
|
||||
assign gt_rxd[15] = gt0_rxdata_i[16];
|
||||
assign gt_rxd[16] = gt0_rxdata_i[15];
|
||||
assign gt_rxd[17] = gt0_rxdata_i[14];
|
||||
assign gt_rxd[18] = gt0_rxdata_i[13];
|
||||
assign gt_rxd[19] = gt0_rxdata_i[12];
|
||||
assign gt_rxd[20] = gt0_rxdata_i[11];
|
||||
assign gt_rxd[21] = gt0_rxdata_i[10];
|
||||
assign gt_rxd[22] = gt0_rxdata_i[9 ];
|
||||
assign gt_rxd[23] = gt0_rxdata_i[8 ];
|
||||
assign gt_rxd[24] = gt0_rxdata_i[7 ];
|
||||
assign gt_rxd[25] = gt0_rxdata_i[6 ];
|
||||
assign gt_rxd[26] = gt0_rxdata_i[5 ];
|
||||
assign gt_rxd[27] = gt0_rxdata_i[4 ];
|
||||
assign gt_rxd[28] = gt0_rxdata_i[3 ];
|
||||
assign gt_rxd[29] = gt0_rxdata_i[2 ];
|
||||
assign gt_rxd[30] = gt0_rxdata_i[1 ];
|
||||
assign gt_rxd[31] = gt0_rxdata_i[0 ];
|
||||
assign gt_rxc = {4'b0000, gt0_rxheadervalid_i,gt0_rxdatavalid_i, gt0_rxheader_i[0], gt0_rxheader_i[1]};
|
||||
|
||||
always @(posedge rxclk322) begin
|
||||
gt_rxc_d1 <= gt_rxc;
|
||||
gt_rxd_d1 <= gt_rxd;
|
||||
gt0_rxresetdone_i_regrx322 <= gt0_rxresetdone_i;
|
||||
end
|
||||
|
||||
// Asynch reset synchronizer registers
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg areset_q1_clk0_refclk_i_bufh_tmp;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg areset_q1_clk0_refclk_i_bufh;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg areset_gt0_rxusrclk2_i_tmp;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg areset_gt0_rxusrclk2_i;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg areset_clk156_tmp;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg areset_clk156;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg cable_pull_reset_rising_gt0_rxusrclk2_i_tmp;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg cable_pull_reset_rising_gt0_rxusrclk2_i;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg cable_unpull_reset_rising_gt0_rxusrclk2_i_tmp;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg cable_unpull_reset_rising_gt0_rxusrclk2_i;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg pma_resetout_rising_gt0_rxusrclk2_i_tmp;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg pma_resetout_rising_gt0_rxusrclk2_i;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg gt0_qplllock_i_gt0_rxusrclk2_i_tmp;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg gt0_qplllock_i_gt0_rxusrclk2_i;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg gt0_qplllock_i_gt0_txusrclk2_i_tmp;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg gt0_qplllock_i_gt0_txusrclk2_i;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg mmcm_locked_clk156_tmp;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg mmcm_locked_clk156;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg gt0_gtrxreset_i_gt0_rxusrclk2_i_tmp;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg gt0_gtrxreset_i_gt0_rxusrclk2_i;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg gt0_gttxreset_i_gt0_txusrclk2_i_tmp;
|
||||
(* ASYNC_REG = "TRUE" *)
|
||||
reg gt0_gttxreset_i_gt0_txusrclk2_i;
|
||||
|
||||
// Asynch reset synchronizers
|
||||
always @(posedge areset or posedge q1_clk0_refclk_i_bufh)
|
||||
begin
|
||||
if(areset)
|
||||
begin
|
||||
areset_q1_clk0_refclk_i_bufh_tmp <= 1'b1;
|
||||
areset_q1_clk0_refclk_i_bufh <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
areset_q1_clk0_refclk_i_bufh_tmp <= 1'b0;
|
||||
areset_q1_clk0_refclk_i_bufh <= areset_q1_clk0_refclk_i_bufh_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge areset or posedge gt0_rxusrclk2_i)
|
||||
begin
|
||||
if(areset)
|
||||
begin
|
||||
areset_gt0_rxusrclk2_i_tmp <= 1'b1;
|
||||
areset_gt0_rxusrclk2_i <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
areset_gt0_rxusrclk2_i_tmp <= 1'b0;
|
||||
areset_gt0_rxusrclk2_i <= areset_gt0_rxusrclk2_i_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge areset or posedge clk156)
|
||||
begin
|
||||
if(areset)
|
||||
begin
|
||||
areset_clk156_tmp <= 1'b1;
|
||||
areset_clk156 <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
areset_clk156_tmp <= 1'b0;
|
||||
areset_clk156 <= areset_clk156_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge cable_pull_reset_rising or posedge gt0_rxusrclk2_i)
|
||||
begin
|
||||
if(cable_pull_reset_rising)
|
||||
begin
|
||||
cable_pull_reset_rising_gt0_rxusrclk2_i_tmp <= 1'b1;
|
||||
cable_pull_reset_rising_gt0_rxusrclk2_i <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
cable_pull_reset_rising_gt0_rxusrclk2_i_tmp <= 1'b0;
|
||||
cable_pull_reset_rising_gt0_rxusrclk2_i <= cable_pull_reset_rising_gt0_rxusrclk2_i_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge cable_unpull_reset_rising or posedge gt0_rxusrclk2_i)
|
||||
begin
|
||||
if(cable_unpull_reset_rising)
|
||||
begin
|
||||
cable_unpull_reset_rising_gt0_rxusrclk2_i_tmp <= 1'b1;
|
||||
cable_unpull_reset_rising_gt0_rxusrclk2_i <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
cable_unpull_reset_rising_gt0_rxusrclk2_i_tmp <= 1'b0;
|
||||
cable_unpull_reset_rising_gt0_rxusrclk2_i <= cable_unpull_reset_rising_gt0_rxusrclk2_i_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pma_resetout_rising or posedge gt0_rxusrclk2_i)
|
||||
begin
|
||||
if(pma_resetout_rising)
|
||||
begin
|
||||
pma_resetout_rising_gt0_rxusrclk2_i_tmp <= 1'b1;
|
||||
pma_resetout_rising_gt0_rxusrclk2_i <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
pma_resetout_rising_gt0_rxusrclk2_i_tmp <= 1'b0;
|
||||
pma_resetout_rising_gt0_rxusrclk2_i <= pma_resetout_rising_gt0_rxusrclk2_i_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge gt0_qplllock_i or posedge gt0_rxusrclk2_i)
|
||||
begin
|
||||
if(!gt0_qplllock_i)
|
||||
begin
|
||||
gt0_qplllock_i_gt0_rxusrclk2_i_tmp <= 1'b0;
|
||||
gt0_qplllock_i_gt0_rxusrclk2_i <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
gt0_qplllock_i_gt0_rxusrclk2_i_tmp <= 1'b1;
|
||||
gt0_qplllock_i_gt0_rxusrclk2_i <= gt0_qplllock_i_gt0_rxusrclk2_i_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge gt0_qplllock_i or posedge gt0_txusrclk2_i)
|
||||
begin
|
||||
if(!gt0_qplllock_i)
|
||||
begin
|
||||
gt0_qplllock_i_gt0_txusrclk2_i_tmp <= 1'b0;
|
||||
gt0_qplllock_i_gt0_txusrclk2_i <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
gt0_qplllock_i_gt0_txusrclk2_i_tmp <= 1'b1;
|
||||
gt0_qplllock_i_gt0_txusrclk2_i <= gt0_qplllock_i_gt0_txusrclk2_i_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge mmcm_locked or posedge clk156)
|
||||
begin
|
||||
if(!mmcm_locked)
|
||||
begin
|
||||
mmcm_locked_clk156_tmp <= 1'b0;
|
||||
mmcm_locked_clk156 <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
mmcm_locked_clk156_tmp <= 1'b1;
|
||||
mmcm_locked_clk156 <= mmcm_locked_clk156_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge gt0_gtrxreset_i or posedge gt0_rxusrclk2_i)
|
||||
begin
|
||||
if(gt0_gtrxreset_i)
|
||||
begin
|
||||
gt0_gtrxreset_i_gt0_rxusrclk2_i_tmp <= 1'b1;
|
||||
gt0_gtrxreset_i_gt0_rxusrclk2_i <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
gt0_gtrxreset_i_gt0_rxusrclk2_i_tmp <= 1'b0;
|
||||
gt0_gtrxreset_i_gt0_rxusrclk2_i <= gt0_gtrxreset_i_gt0_rxusrclk2_i_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge gt0_gttxreset_i or posedge gt0_txusrclk2_i)
|
||||
begin
|
||||
if(gt0_gttxreset_i)
|
||||
begin
|
||||
gt0_gttxreset_i_gt0_txusrclk2_i_tmp <= 1'b1;
|
||||
gt0_gttxreset_i_gt0_txusrclk2_i <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
gt0_gttxreset_i_gt0_txusrclk2_i_tmp <= 1'b0;
|
||||
gt0_gttxreset_i_gt0_txusrclk2_i <= gt0_gttxreset_i_gt0_txusrclk2_i_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
// Reset logic from the gtwizard top level output file....
|
||||
// Adapt the reset_counter to count clk156 ticks.
|
||||
// 128 ticks at 6.4ns period will be >> 500 ns.
|
||||
// Removed all 'after DLY' text.
|
||||
|
||||
always @(posedge q1_clk0_refclk_i_bufh or posedge areset_q1_clk0_refclk_i_bufh)
|
||||
begin
|
||||
if (areset_q1_clk0_refclk_i_bufh == 1'b1)
|
||||
reset_counter <= 8'b0;
|
||||
else if (!reset_counter[7])
|
||||
reset_counter <= reset_counter + 1'b1;
|
||||
else
|
||||
reset_counter <= reset_counter;
|
||||
end
|
||||
|
||||
always @(posedge q1_clk0_refclk_i_bufh)
|
||||
begin
|
||||
if(!reset_counter[7])
|
||||
reset_pulse <= 4'b1110;
|
||||
else
|
||||
reset_pulse <= {1'b0, reset_pulse[3:1]};
|
||||
end
|
||||
|
||||
// Delay the assertion of RXUSERRDY by the given amount
|
||||
always @(posedge gt0_rxusrclk2_i or posedge gt0_gtrxreset_i_gt0_rxusrclk2_i or negedge gt0_qplllock_i_gt0_rxusrclk2_i)
|
||||
begin
|
||||
if(!gt0_qplllock_i_gt0_rxusrclk2_i || gt0_gtrxreset_i_gt0_rxusrclk2_i)
|
||||
rxuserrdy_counter <= 20'h0;
|
||||
else if (!(rxuserrdy_counter == RXRESETTIME))
|
||||
rxuserrdy_counter <= rxuserrdy_counter + 1'b1;
|
||||
else
|
||||
rxuserrdy_counter <= rxuserrdy_counter;
|
||||
end
|
||||
|
||||
assign GTTXRESET_IN = reset_pulse[0];
|
||||
assign GTRXRESET_IN = reset_pulse[0];
|
||||
|
||||
assign QPLLRESET_IN = reset_pulse[0];
|
||||
|
||||
assign gt0_rxuserrdy_i = gt0_rxuserrdy_r;
|
||||
assign gt0_txuserrdy_i = gt0_txuserrdy_r;
|
||||
|
||||
always @(posedge gt0_rxusrclk2_i or posedge gt0_gtrxreset_i_gt0_rxusrclk2_i)
|
||||
begin
|
||||
if(gt0_gtrxreset_i_gt0_rxusrclk2_i)
|
||||
gt0_rxuserrdy_r <= 1'b0;
|
||||
else if(rxuserrdy_counter == RXRESETTIME)
|
||||
gt0_rxuserrdy_r <= 1'b1;
|
||||
else
|
||||
gt0_rxuserrdy_r <= gt0_rxuserrdy_r;
|
||||
end
|
||||
|
||||
always @(posedge gt0_txusrclk2_i or posedge gt0_gttxreset_i_gt0_txusrclk2_i)
|
||||
begin
|
||||
if(gt0_gttxreset_i_gt0_txusrclk2_i)
|
||||
gt0_txuserrdy_r <= 1'b0;
|
||||
else
|
||||
gt0_txuserrdy_r <= gt0_qplllock_i_gt0_txusrclk2_i;
|
||||
end
|
||||
|
||||
// Create a watchdog which samples 4 bits from the gt_rxd vector and checks that it does
|
||||
// vary from a 1010 or 0101 or 0000 pattern. If not then there may well have been a cable pull
|
||||
// and the gt rx side needs to be reset.
|
||||
always @(posedge gt0_rxusrclk2_i or posedge cable_pull_reset_rising_gt0_rxusrclk2_i)
|
||||
begin
|
||||
if(cable_pull_reset_rising_gt0_rxusrclk2_i)
|
||||
begin
|
||||
cable_pull_watchdog_event <= 2'b00;
|
||||
cable_pull_watchdog <= 20'h20000; // reset the watchdog
|
||||
cable_pull_reset <= 1'b0;
|
||||
rx_sample <= 4'b0;
|
||||
rx_sample_prev <= 4'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// Sample 4 bits of the gt_rxd vector
|
||||
rx_sample <= gt_rxd[7:4];
|
||||
rx_sample_prev <= rx_sample;
|
||||
|
||||
if(!cable_pull_reset && !cable_is_pulled && gt0_rxresetdone_i_regrx322)
|
||||
begin
|
||||
// If those 4 bits do not look like the cable-pull behaviour, increment the event counter
|
||||
if(!(rx_sample == 4'b1010) && !(rx_sample == 4'b0101) && !(rx_sample == 4'b0000) && !(rx_sample == rx_sample_prev)) // increment the event counter
|
||||
cable_pull_watchdog_event <= cable_pull_watchdog_event + 1;
|
||||
else // we are seeing what may be a cable pull
|
||||
cable_pull_watchdog_event <= 2'b00;
|
||||
|
||||
|
||||
if(cable_pull_watchdog_event == 2'b10) // Two consecutive events which look like the cable is attached
|
||||
begin
|
||||
cable_pull_watchdog <= 20'h20000; // reset the watchdog
|
||||
cable_pull_watchdog_event <= 2'b00;
|
||||
end
|
||||
else
|
||||
cable_pull_watchdog <= cable_pull_watchdog - 1;
|
||||
|
||||
|
||||
if(~|cable_pull_watchdog)
|
||||
cable_pull_reset <= 1'b1; // Hit GTRXRESET!
|
||||
else
|
||||
cable_pull_reset <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
if(mmcm_locked == 1'b1) begin
|
||||
cable_pull_reset_reg <= cable_pull_reset;
|
||||
cable_pull_reset_reg_reg <= cable_pull_reset_reg;
|
||||
cable_pull_reset_rising <= cable_pull_reset_reg && !cable_pull_reset_reg_reg;
|
||||
cable_pull_reset_rising_reg <= cable_pull_reset_rising;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge gt0_rxusrclk2_i or posedge areset_gt0_rxusrclk2_i or posedge pma_resetout_rising_gt0_rxusrclk2_i)
|
||||
begin
|
||||
if(areset_gt0_rxusrclk2_i || pma_resetout_rising_gt0_rxusrclk2_i)
|
||||
cable_unpull_enable <= 1'b0;
|
||||
else if(cable_pull_reset) // Cable pull has been detected - enable cable unpull counter
|
||||
cable_unpull_enable <= 1'b1;
|
||||
else if(cable_unpull_reset) // Cable has been detected as being plugged in again
|
||||
cable_unpull_enable <= 1'b0;
|
||||
else
|
||||
cable_unpull_enable <= cable_unpull_enable;
|
||||
end
|
||||
|
||||
// Look for data on the line which does NOT look like the cable is still pulled
|
||||
// a set of 1024 non-1010 or 0101 or 0000 samples within 128k samples suggests that the cable is in.
|
||||
always @(posedge gt0_rxusrclk2_i or posedge cable_unpull_reset_rising_gt0_rxusrclk2_i)
|
||||
begin
|
||||
if(cable_unpull_reset_rising_gt0_rxusrclk2_i)
|
||||
begin
|
||||
cable_unpull_reset <= 1'b0;
|
||||
cable_unpull_watchdog_event <= 11'b0; // reset the event counter
|
||||
cable_unpull_watchdog <= 20'h20000; // reset the watchdog window
|
||||
end
|
||||
else
|
||||
begin
|
||||
if(!cable_unpull_reset && cable_is_pulled && gt0_rxresetdone_i_regrx322)
|
||||
begin
|
||||
// If those 4 bits do not look like the cable-pull behaviour, increment the event counter
|
||||
if(!(rx_sample == 4'b1010) && !(rx_sample == 4'b0101) && !(rx_sample == 4'b0000) && !(rx_sample == rx_sample_prev)) // increment the event counter
|
||||
cable_unpull_watchdog_event <= cable_unpull_watchdog_event + 1;
|
||||
|
||||
|
||||
if(cable_unpull_watchdog_event[10] == 1'b1) // Detected 1k 'valid' rx data words within 128k words
|
||||
begin
|
||||
cable_unpull_reset <= 1'b1; // Hit GTRXRESET again!
|
||||
cable_unpull_watchdog <= 20'h20000; // reset the watchdog window
|
||||
end
|
||||
else
|
||||
cable_unpull_watchdog <= cable_unpull_watchdog - 1;
|
||||
|
||||
if(~|cable_unpull_watchdog)
|
||||
begin
|
||||
cable_unpull_watchdog <= 20'h20000; // reset the watchdog window
|
||||
cable_unpull_watchdog_event <= 11'b0; // reset the event counter
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
if(mmcm_locked == 1'b1) begin
|
||||
cable_unpull_reset_reg <= cable_unpull_reset;
|
||||
cable_unpull_reset_reg_reg <= cable_unpull_reset_reg;
|
||||
cable_unpull_reset_rising <= cable_unpull_reset_reg && !cable_unpull_reset_reg_reg;
|
||||
cable_unpull_reset_rising_reg <= cable_unpull_reset_rising;
|
||||
end
|
||||
end
|
||||
|
||||
// Create the local cable_is_pulled signal
|
||||
assign cable_is_pulled = cable_unpull_enable;
|
||||
|
||||
// Create the signal_detect signal as an AND of the external signal and (not) the local cable_is_pulled
|
||||
assign signal_detect_comb = signal_detect && !cable_is_pulled;
|
||||
|
||||
|
||||
always @(posedge areset_clk156 or posedge clk156 or negedge mmcm_locked_clk156)
|
||||
begin
|
||||
if(areset_clk156 || !mmcm_locked_clk156)
|
||||
pma_resetout_reg <= 1'b0;
|
||||
else
|
||||
pma_resetout_reg <= pma_resetout;
|
||||
end
|
||||
|
||||
assign pma_resetout_rising = pma_resetout && !pma_resetout_reg;
|
||||
|
||||
always @(posedge areset_clk156 or posedge clk156 or negedge mmcm_locked_clk156)
|
||||
begin
|
||||
if(areset_clk156 || !mmcm_locked_clk156)
|
||||
pcs_resetout_reg <= 1'b0;
|
||||
else
|
||||
pcs_resetout_reg <= pcs_resetout;
|
||||
end
|
||||
|
||||
assign pcs_resetout_rising = pcs_resetout && !pcs_resetout_reg;
|
||||
|
||||
|
||||
// Incorporate the pma_resetout_rising and cable_pull/unpull_reset_rising bits generated in code below.
|
||||
assign gt0_gtrxreset_i = (GTRXRESET_IN || !gt0_qplllock_i || pma_resetout_rising ||
|
||||
cable_pull_reset_rising_reg || cable_unpull_reset_rising_reg) && reset_counter[7];
|
||||
assign gt0_gttxreset_i = (GTTXRESET_IN || !gt0_qplllock_i || pma_resetout_rising) && reset_counter[7];
|
||||
assign gt0_qpllreset_i = QPLLRESET_IN;
|
||||
|
||||
assign gt0_rxpcsreset_i = pcs_resetout_rising;
|
||||
assign gt0_txpcsreset_i = pcs_resetout_rising;
|
||||
|
||||
// reset the GT RX Buffer when over/underflowing
|
||||
always @(posedge gt0_rxusrclk2_i)
|
||||
begin
|
||||
if(gt0_rxbufstatus_i[2] == 1'b1 && gt0_rxresetdone_i_regrx322)
|
||||
gt0_rxbufreset_i <= 1'b1;
|
||||
else
|
||||
gt0_rxbufreset_i <= 1'b0;
|
||||
end
|
||||
|
||||
// As generated by the GT Wizard - cut from _top level in eg design dir
|
||||
ten_gig_eth_pcs_pma_GT_USRCLK_SOURCE gt_usrclk_source
|
||||
(
|
||||
// IJB. Remove IBUFDS_GTE2 from 10G PHY hierarchy so that it can be shared.
|
||||
//
|
||||
// .Q1_CLK0_GTREFCLK_PAD_N_IN (Q1_CLK0_GTREFCLK_PAD_N_IN),
|
||||
// .Q1_CLK0_GTREFCLK_PAD_P_IN (Q1_CLK0_GTREFCLK_PAD_P_IN),
|
||||
// .Q1_CLK0_GTREFCLK_OUT (q1_clk0_refclk_i),
|
||||
|
||||
.GT0_TXUSRCLK_OUT (gt0_txusrclk_i),
|
||||
.GT0_TXUSRCLK2_OUT (gt0_txusrclk2_i),
|
||||
.GT0_TXOUTCLK_IN (gt0_txoutclk_i),
|
||||
.GT0_RXUSRCLK_OUT (gt0_rxusrclk_i),
|
||||
.GT0_RXUSRCLK2_OUT (gt0_rxusrclk2_i),
|
||||
.GT0_RXOUTCLK_IN (gt0_rxoutclk_i),
|
||||
.DRPCLK_IN (tied_to_ground_i),
|
||||
.DRPCLK_OUT ()
|
||||
);
|
||||
|
||||
// MMCM to generate both clk156 and dclk
|
||||
MMCME2_BASE #
|
||||
(
|
||||
.BANDWIDTH ("OPTIMIZED"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT_F (4.0),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKOUT0_DIVIDE_F (4.000),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKIN1_PERIOD (6.400),
|
||||
.CLKOUT1_DIVIDE (8),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.REF_JITTER1 (0.010)
|
||||
)
|
||||
clkgen_i
|
||||
(
|
||||
.CLKFBIN(clkfbout),
|
||||
.CLKIN1(q1_clk0_refclk_i_bufh),
|
||||
.PWRDWN(1'b0),
|
||||
.RST(!gt0_qplllock_i),
|
||||
.CLKFBOUT(clkfbout),
|
||||
.CLKOUT0(clk156_buf),
|
||||
.CLKOUT1(dclk_buf),
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
BUFG bufg_inst
|
||||
(
|
||||
// .CE (tied_to_vcc_i),
|
||||
.I (q1_clk0_refclk_i),
|
||||
.O (q1_clk0_refclk_i_bufh)
|
||||
);
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
BUFG clk156_bufg_inst
|
||||
(
|
||||
.I (clk156_buf),
|
||||
.O (clk156)
|
||||
);
|
||||
|
||||
BUFG dclk_bufg_inst
|
||||
(
|
||||
.I (dclk_buf),
|
||||
.O (dclk)
|
||||
);
|
||||
|
||||
// As generated by the GT Wizard - cut from _top level in eg design dir
|
||||
// Use this example as a template for any updates - some signal names in
|
||||
// port mappings may have been changed from the GT wizard output
|
||||
ten_gig_eth_pcs_pma_gtwizard_10gbaser #
|
||||
(
|
||||
.WRAPPER_SIM_GTRESET_SPEEDUP (EXAMPLE_SIM_GTRESET_SPEEDUP)
|
||||
)
|
||||
gtwizard_10gbaser_i
|
||||
(
|
||||
//_____________________________________________________________________
|
||||
//_____________________________________________________________________
|
||||
//
|
||||
|
||||
//-------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
|
||||
.GT0_DRPADDR_IN (gt0_drpaddr_i[8:0]),
|
||||
.GT0_DRPCLK_IN (gt0_drpclk_i),
|
||||
.GT0_DRPDI_IN (gt0_drpdi_i),
|
||||
.GT0_DRPDO_OUT (gt0_drpdo_i),
|
||||
.GT0_DRPEN_IN (gt0_drpen_i),
|
||||
.GT0_DRPRDY_OUT (gt0_drprdy_i),
|
||||
.GT0_DRPWE_IN (gt0_drpwe_i),
|
||||
//----------------------------- Eye Scan Ports -----------------------------
|
||||
.GT0_EYESCANDATAERROR_OUT (gt0_eyescandataerror_i),
|
||||
//---------------------- Loopback and Powerdown Ports ----------------------
|
||||
.GT0_LOOPBACK_IN (gt0_loopback_i),
|
||||
//----------------------------- Receive Ports ------------------------------
|
||||
.GT0_RXUSERRDY_IN (gt0_rxuserrdy_i),
|
||||
//------------ Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
|
||||
.GT0_RXDATAVALID_OUT (gt0_rxdatavalid_i),
|
||||
.GT0_RXGEARBOXSLIP_IN (gt0_rxgearboxslip_i),
|
||||
.GT0_RXHEADER_OUT (gt0_rxheader_i),
|
||||
.GT0_RXHEADERVALID_OUT (gt0_rxheadervalid_i),
|
||||
//--------------------- Receive Ports - PRBS Detection ---------------------
|
||||
.GT0_RXPRBSCNTRESET_IN (gt0_clear_rx_prbs_err_count_i),
|
||||
.GT0_RXPRBSERR_OUT (),
|
||||
.GT0_RXPRBSSEL_IN ({rx_prbs31_en,2'b00}),
|
||||
//----------------- Receive Ports - RX Data Path interface -----------------
|
||||
.GT0_GTRXRESET_IN (gt0_gtrxreset_i),
|
||||
.GT0_RXDATA_OUT (gt0_rxdata_i),
|
||||
.GT0_RXOUTCLK_OUT (gt0_rxoutclk_i),
|
||||
.GT0_RXPCSRESET_IN (gt0_rxpcsreset_i),
|
||||
.GT0_RXUSRCLK_IN (gt0_rxusrclk_i),
|
||||
.GT0_RXUSRCLK2_IN (gt0_rxusrclk2_i),
|
||||
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
||||
.GT0_GTXRXN_IN (RXN_IN),
|
||||
.GT0_GTXRXP_IN (RXP_IN),
|
||||
.GT0_RXCDRLOCK_OUT (),
|
||||
.GT0_RXELECIDLE_OUT (),
|
||||
.GT0_RXLPMEN_IN (1'b0),
|
||||
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
|
||||
.GT0_RXBUFRESET_IN (gt0_rxbufreset_i),
|
||||
.GT0_RXBUFSTATUS_OUT (gt0_rxbufstatus_i),
|
||||
//---------------------- Receive Ports - RX PLL Ports ----------------------
|
||||
.GT0_RXRESETDONE_OUT (gt0_rxresetdone_i),
|
||||
//----------------------------- Transmit Ports -----------------------------
|
||||
.GT0_TXUSERRDY_IN (gt0_txuserrdy_i),
|
||||
//------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
|
||||
.GT0_TXHEADER_IN (gt0_txheader_i),
|
||||
.GT0_TXSEQUENCE_IN (gt0_txsequence_i),
|
||||
//---------------- Transmit Ports - TX Data Path interface -----------------
|
||||
.GT0_GTTXRESET_IN (gt0_gttxreset_i),
|
||||
.GT0_TXDATA_IN (gt0_txdata_i),
|
||||
.GT0_TXOUTCLK_OUT (gt0_txoutclk_i),
|
||||
.GT0_TXOUTCLKFABRIC_OUT (gt0_txoutclkfabric_i),
|
||||
.GT0_TXOUTCLKPCS_OUT (gt0_txoutclkpcs_i),
|
||||
.GT0_TXPCSRESET_IN (gt0_txpcsreset_i),
|
||||
.GT0_TXUSRCLK_IN (gt0_txusrclk_i),
|
||||
.GT0_TXUSRCLK2_IN (gt0_txusrclk2_i),
|
||||
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
|
||||
.GT0_GTXTXN_OUT (TXN_OUT),
|
||||
.GT0_GTXTXP_OUT (TXP_OUT),
|
||||
.GT0_TXINHIBIT_IN (tx_disable),
|
||||
.GT0_TXPRECURSOR_IN (5'b0),
|
||||
.GT0_TXPOSTCURSOR_IN (5'b0),
|
||||
.GT0_TXMAINCURSOR_IN (7'b0),
|
||||
//--------------------- Transmit Ports - TX PLL Ports ----------------------
|
||||
.GT0_TXRESETDONE_OUT (gt0_txresetdone_i),
|
||||
//------------------- Transmit Ports - TX PRBS Generator -------------------
|
||||
.GT0_TXPRBSSEL_IN ({tx_prbs31_en,2'b00}),
|
||||
|
||||
|
||||
|
||||
//____________________________COMMON PORTS________________________________
|
||||
//-------------------- Common Block - Ref Clock Ports ---------------------
|
||||
.GT0_GTREFCLK0_COMMON_IN (q1_clk0_refclk_i),
|
||||
//----------------------- Common Block - QPLL Ports ------------------------
|
||||
.GT0_QPLLLOCK_OUT (gt0_qplllock_i),
|
||||
.GT0_QPLLLOCKDETCLK_IN (tied_to_ground_i),
|
||||
.GT0_QPLLREFCLKLOST_OUT (),
|
||||
.GT0_QPLLRESET_IN (gt0_qpllreset_i)
|
||||
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
+105
@@ -0,0 +1,105 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// Title : Verilog component declaration for block level 10GBASE-R core
|
||||
// Project : 10 Gigabit Ethernet PCS PMA Core
|
||||
// File : ten_gig_eth_pcs_pma_mod.v
|
||||
// Author : Xilinx Inc.
|
||||
// Description: This module holds the top level component declaration for the
|
||||
// 10Gb/E PCS/PMA core.
|
||||
//---------------------------------------------------------------------------
|
||||
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
module ten_gig_eth_pcs_pma
|
||||
(
|
||||
input reset,
|
||||
input txreset322,
|
||||
input rxreset322,
|
||||
input dclk_reset,
|
||||
output pma_resetout,
|
||||
output pcs_resetout,
|
||||
input clk156,
|
||||
input txusrclk2,
|
||||
input rxusrclk2,
|
||||
input dclk,
|
||||
|
||||
input [63 : 0] xgmii_txd,
|
||||
input [7 : 0] xgmii_txc,
|
||||
output [63 : 0] xgmii_rxd,
|
||||
output [7 : 0] xgmii_rxc,
|
||||
|
||||
input mdc,
|
||||
input mdio_in,
|
||||
output mdio_out,
|
||||
output mdio_tri,
|
||||
input [4 : 0] prtad,
|
||||
output [7 : 0] core_status,
|
||||
input [2 : 0] pma_pmd_type,
|
||||
output drp_req,
|
||||
input drp_gnt,
|
||||
output drp_den,
|
||||
output drp_dwe,
|
||||
output [15:0] drp_daddr,
|
||||
input drp_drdy,
|
||||
input [15:0] drp_drpdo,
|
||||
output [15:0] drp_di,
|
||||
|
||||
output [31 : 0] gt_txd,
|
||||
output [7 : 0] gt_txc,
|
||||
input [31 : 0] gt_rxd,
|
||||
input [7 : 0] gt_rxc,
|
||||
output gt_slip,
|
||||
|
||||
input resetdone,
|
||||
output tx_prbs31_en,
|
||||
output rx_prbs31_en,
|
||||
output clear_rx_prbs_err_count,
|
||||
output [2 : 0] loopback_ctrl,
|
||||
|
||||
input signal_detect,
|
||||
input tx_fault,
|
||||
output tx_disable);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,85 @@
|
||||
## (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
|
||||
##
|
||||
## This file contains confidential and proprietary information
|
||||
## of Xilinx, Inc. and is protected under U.S. and
|
||||
## international copyright and other intellectual property
|
||||
## laws.
|
||||
##
|
||||
## DISCLAIMER
|
||||
## This disclaimer is not a license and does not grant any
|
||||
## rights to the materials distributed herewith. Except as
|
||||
## otherwise provided in a valid license issued to you by
|
||||
## Xilinx, and to the maximum extent permitted by applicable
|
||||
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
## (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
## including negligence, or under any other theory of
|
||||
## liability) for any loss or damage of any kind or nature
|
||||
## related to, arising under or in connection with these
|
||||
## materials, including for any direct, or any indirect,
|
||||
## special, incidental, or consequential loss or damage
|
||||
## (including loss of data, profits, goodwill, or any type of
|
||||
## loss or damage suffered as a result of any action brought
|
||||
## by a third party) even if such damage or loss was
|
||||
## reasonably foreseeable or Xilinx had been advised of the
|
||||
## possibility of the same.
|
||||
##
|
||||
## CRITICAL APPLICATIONS
|
||||
## Xilinx products are not designed or intended to be fail-
|
||||
## safe, or for use in any application requiring fail-safe
|
||||
## performance, such as life-support or safety devices or
|
||||
## systems, Class III medical devices, nuclear facilities,
|
||||
## applications related to the deployment of airbags, or any
|
||||
## other applications that could lead to death, personal
|
||||
## injury, or severe property or environmental damage
|
||||
## (individually and collectively, "Critical
|
||||
## Applications"). Customer assumes the sole risk and
|
||||
## liability of any use of Xilinx products in Critical
|
||||
## Applications, subject only to applicable laws and
|
||||
## regulations governing limitations on product liability.
|
||||
##
|
||||
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
## PART OF THIS FILE AT ALL TIMES.
|
||||
#######################################################################
|
||||
# Clock frequencies/periods and clock management #
|
||||
# #
|
||||
#######################################################################
|
||||
#NET "*gt0_rxoutclk_i" TNM_NET="rxoutclk";
|
||||
#TIMESPEC "TS_rxoutclk" = PERIOD "rxoutclk" 3103 ps;
|
||||
#NET "*gt0_txoutclk_i" TNM_NET="txoutclk";
|
||||
#TIMESPEC "TS_txoutclk" = PERIOD "txoutclk" 3103 ps;
|
||||
# Edit these constraints to select the correct transceiver for your design
|
||||
#INST *gtxe2_i LOC=GTXE2_CHANNEL_X0Y12;
|
||||
#INST *gtxe2_i LOC=GTXE2_CHANNEL_X0Y0;
|
||||
#INST "*gtxe2_common_0_i" LOC = "GTXE2_COMMON_X0Y0";
|
||||
# JAB moved this to individual port ucfs in top level
|
||||
#INST "*port0/*gtxe2_i" LOC=GTXE2_CHANNEL_X0Y0;
|
||||
#INST "*port0/*gtxe2_common_0_i" LOC = "GTXE2_COMMON_X0Y0";
|
||||
#INST "*port1/*gtxe2_i" LOC=GTXE2_CHANNEL_X0Y4;
|
||||
#INST "*port1/*gtxe2_common_0_i" LOC = "GTXE2_COMMON_X0Y1";
|
||||
|
||||
NET "*cable_pull_reset" MAXDELAY = 2.0 ns;
|
||||
NET "*cable_unpull_reset" MAXDELAY = 2.0 ns;
|
||||
|
||||
##################################################################
|
||||
# Elastic Buffer-related constraints #
|
||||
##################################################################
|
||||
NET "*elastic_buffer_i*rd_truegray<?>" MAXDELAY = 6.0 ns;
|
||||
NET "*elastic_buffer_i?can_insert_wra" TIG;
|
||||
NET "*wr_gray*<?>" MAXDELAY = 6.0 ns;
|
||||
NET "*rd_lastgray*<?>" MAXDELAY = 6.0 ns;
|
||||
###################################################################
|
||||
NET "*sfp_clk" TNM_NET="refclk";
|
||||
NET "*clk156_buf*" TNM_NET="clk156";
|
||||
NET "*rxclk322" TNM_NET="rxusrclk2";
|
||||
NET "*txclk322" TNM_NET="txclk322";
|
||||
|
||||
TIMESPEC "TS_rxusrclk2_to_clk156" = FROM rxusrclk2 TO clk156 TIG;
|
||||
TIMESPEC "TS_rxusrclk2_to_txclk322" = FROM rxusrclk2 TO txclk322 TIG;
|
||||
TIMESPEC "TS_clk156_to_txclk322" = FROM clk156 TO txclk322 TIG;
|
||||
TIMESPEC "TS_clk156_to_refclk" = FROM clk156 TO refclk TIG;
|
||||
TIMESPEC "TS_txclk322_to_clk156" = FROM txclk322 TO clk156 TIG;
|
||||
TIMESPEC "TS_rxusrclk2_to_refclk" = FROM rxusrclk2 TO refclk TIG;
|
||||
@@ -0,0 +1,276 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// Title : Example Design level wrapper
|
||||
// Project : 10GBASE-R
|
||||
//-----------------------------------------------------------------------------
|
||||
// File : ten_gig_eth_pcs_pma_example_design.v
|
||||
//-----------------------------------------------------------------------------
|
||||
// Description: This file is a wrapper for the 10GBASE-R core; it contains all
|
||||
// of the clock buffers required for implementing the block level
|
||||
//-----------------------------------------------------------------------------
|
||||
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
//
|
||||
// NOTE!: Modified example design to create x300 top level
|
||||
// for this IP block.
|
||||
//
|
||||
module ten_gig_eth_pcs_pma_x300_top
|
||||
(
|
||||
// input refclk_p,
|
||||
// input refclk_n,
|
||||
input refclk156,
|
||||
input refclk156_buf,
|
||||
output clk156,
|
||||
input reset,
|
||||
input [63 : 0] xgmii_txd,
|
||||
input [7 : 0] xgmii_txc,
|
||||
output reg [63 : 0] xgmii_rxd,
|
||||
output reg [7 : 0] xgmii_rxc,
|
||||
// output xgmii_rx_clk, //IJB
|
||||
output txp,
|
||||
output txn,
|
||||
input rxp,
|
||||
input rxn,
|
||||
input mdc,
|
||||
input mdio_in,
|
||||
output reg mdio_out,
|
||||
output reg mdio_tri,
|
||||
input [4 : 0] prtad,
|
||||
output [7:0] core_status,
|
||||
output resetdone,
|
||||
input signal_detect,
|
||||
input tx_fault,
|
||||
output tx_disable);
|
||||
|
||||
// Signal declarations
|
||||
wire clk156;
|
||||
|
||||
// Sync the global reset to the relevant clocks
|
||||
reg core_reset_tx;
|
||||
reg core_reset_rx;
|
||||
reg txreset322;
|
||||
reg rxreset322;
|
||||
reg dclk_reset;
|
||||
|
||||
reg core_reset_tx_tmp;
|
||||
reg core_reset_rx_tmp;
|
||||
reg txreset322_tmp;
|
||||
reg rxreset322_tmp;
|
||||
reg dclk_reset_tmp;
|
||||
|
||||
(* KEEP = "true" *)
|
||||
wire txclk322;
|
||||
wire rxclk322;
|
||||
wire dclk;
|
||||
|
||||
wire tx_resetdone_int;
|
||||
wire rx_resetdone_int;
|
||||
reg [63:0] xgmii_txd_reg;
|
||||
reg [7:0] xgmii_txc_reg;
|
||||
wire [63:0] xgmii_rxd_int;
|
||||
wire [7:0] xgmii_rxc_int;
|
||||
|
||||
wire mdio_out_int;
|
||||
wire mdio_tri_int;
|
||||
|
||||
assign resetdone = tx_resetdone_int && rx_resetdone_int;
|
||||
|
||||
//synthesis attribute async_reg of core_reset_tx_tmp is "true";
|
||||
//synthesis attribute async_reg of core_reset_tx is "true";
|
||||
//synthesis attribute async_reg of core_reset_rx_tmp is "true";
|
||||
//synthesis attribute async_reg of core_reset_rx is "true";
|
||||
always @(posedge reset or posedge clk156)
|
||||
begin
|
||||
if(reset)
|
||||
begin
|
||||
core_reset_tx_tmp <= 1'b1;
|
||||
core_reset_tx <= 1'b1;
|
||||
core_reset_rx_tmp <= 1'b1;
|
||||
core_reset_rx <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// Hold core in reset until everything else is ready...
|
||||
// IJB. Per AR# 53443 changed these lines:
|
||||
// core_reset_tx_tmp <= (!(tx_resetdone_int) || reset ||
|
||||
// tx_fault || !(signal_detect) );
|
||||
core_reset_tx_tmp <= (!(tx_resetdone_int) || reset);
|
||||
|
||||
core_reset_tx <= core_reset_tx_tmp;
|
||||
// core_reset_rx_tmp <= (!(rx_resetdone_int) || reset ||
|
||||
// tx_fault || !(signal_detect) );
|
||||
core_reset_rx_tmp <= (!(rx_resetdone_int) || reset || !(signal_detect));
|
||||
|
||||
core_reset_rx <= core_reset_rx_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
//synthesis attribute async_reg of txreset322_tmp is "true";
|
||||
//synthesis attribute async_reg of txreset322 is "true";
|
||||
always @(posedge reset or posedge txclk322)
|
||||
begin
|
||||
if(reset)
|
||||
begin
|
||||
txreset322_tmp <= 1'b1;
|
||||
txreset322 <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
txreset322_tmp <= core_reset_tx;
|
||||
txreset322 <= txreset322_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
//synthesis attribute async_reg of rxreset322_tmp is "true";
|
||||
//synthesis attribute async_reg of rxreset322 is "true";
|
||||
always @(posedge reset or posedge rxclk322)
|
||||
begin
|
||||
if(reset)
|
||||
begin
|
||||
rxreset322_tmp <= 1'b1;
|
||||
rxreset322 <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
rxreset322_tmp <= core_reset_rx;
|
||||
rxreset322 <= rxreset322_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
//synthesis attribute async_reg of dclk_reset_tmp is "true";
|
||||
//synthesis attribute async_reg of dclk_reset is "true";
|
||||
always @(posedge reset or posedge dclk)
|
||||
begin
|
||||
if(reset)
|
||||
begin
|
||||
dclk_reset_tmp <= 1'b1;
|
||||
dclk_reset <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dclk_reset_tmp <= core_reset_rx;
|
||||
dclk_reset <= dclk_reset_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
// Add a pipeline to the xmgii_tx inputs, to aid timing closure
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
xgmii_txd_reg <= xgmii_txd;
|
||||
xgmii_txc_reg <= xgmii_txc;
|
||||
end
|
||||
|
||||
// Add a pipeline to the xmgii_rx outputs, to aid timing closure
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
xgmii_rxd <= xgmii_rxd_int;
|
||||
xgmii_rxc <= xgmii_rxc_int;
|
||||
end
|
||||
|
||||
// Add a pipeline to the mdio outputs, to aid timing closure
|
||||
// This is safe because the mdio clock is running so slowly
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
mdio_out <= mdio_out_int;
|
||||
mdio_tri <= mdio_tri_int;
|
||||
end
|
||||
|
||||
// Instantiate the 10GBASE-R Block Level
|
||||
|
||||
ten_gig_eth_pcs_pma_block # (
|
||||
.EXAMPLE_SIM_GTRESET_SPEEDUP("TRUE") ) //Does not affect hardware
|
||||
ten_gig_eth_pcs_pma_block
|
||||
(
|
||||
// .refclk_n(refclk_n),
|
||||
// .refclk_p(refclk_p),
|
||||
.refclk156(refclk156),
|
||||
.refclk156_buf(refclk156_buf),
|
||||
.clk156(clk156),
|
||||
.txclk322(txclk322),
|
||||
.rxclk322(rxclk322),
|
||||
.dclk(dclk),
|
||||
.areset(reset),
|
||||
.reset(core_reset_tx),
|
||||
.rxreset322(rxreset322),
|
||||
.txreset322(txreset322),
|
||||
.dclk_reset(dclk_reset),
|
||||
.xgmii_txd(xgmii_txd_reg),
|
||||
.xgmii_txc(xgmii_txc_reg),
|
||||
.xgmii_rxd(xgmii_rxd_int),
|
||||
.xgmii_rxc(xgmii_rxc_int),
|
||||
.txp(txp),
|
||||
.txn(txn),
|
||||
.rxp(rxp),
|
||||
.rxn(rxn),
|
||||
.mdc(mdc),
|
||||
.mdio_in(mdio_in),
|
||||
.mdio_out(mdio_out_int),
|
||||
.mdio_tri(mdio_tri_int),
|
||||
.prtad(prtad),
|
||||
.core_status(core_status),
|
||||
.tx_resetdone(tx_resetdone_int),
|
||||
.rx_resetdone(rx_resetdone_int),
|
||||
.signal_detect(signal_detect),
|
||||
.tx_fault(tx_fault),
|
||||
.tx_disable(tx_disable));
|
||||
|
||||
// assign core_clk156_out = clk156;
|
||||
|
||||
// Not needed in X300
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
|
||||
ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) rx_clk_ddr(
|
||||
.Q(xgmii_rx_clk),
|
||||
.D1(1'b1),
|
||||
.D2(1'b0),
|
||||
.C(clk156),
|
||||
.CE(1'b1),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user