fpga: Multiple X300 FPGA bugfixes and enhancements
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
This commit is contained in:
Ashish Chaudhari
@@ -0,0 +1,405 @@
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version : 2.4
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// \ \ Application : 7 Series FPGAs Transceivers Wizard
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// / / Filename : gige_sfp_mdio_gtwizard.v
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// /___/ /\
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// \ \ / \
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// \___\/\___\
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//
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//
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// Module GTWIZARD (a GT Wrapper)
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// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
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//
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
|
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
|
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
|
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
|
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// (including loss of data, profits, goodwill, or any type of
|
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
|
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
|
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// safe, or for use in any application requiring fail-safe
|
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// performance, such as life-support or safety devices or
|
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
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||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
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||||
// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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`default_nettype wire
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`timescale 1ns / 1ps
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`define DLY #1
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//***************************** Entity Declaration ****************************
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(* CORE_GENERATION_INFO = "gige_sfp_mdio_GTWIZARD,gtwizard_v2_4,{protocol_file=gigabit_ethernet_CC}" *) module gige_sfp_mdio_GTWIZARD #
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(
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// Simulation attributes
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parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false", // Set to "true" to speed up sim reset
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parameter RX_DFE_KL_CFG2_IN = 32'h3010D90C,
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parameter PMA_RSV_IN = 32'h00018480,
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parameter SIM_VERSION = "4.0"
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)
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(
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//-------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
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input [8:0] GT0_DRPADDR_IN,
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input GT0_DRPCLK_IN,
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input [15:0] GT0_DRPDI_IN,
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output [15:0] GT0_DRPDO_OUT,
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input GT0_DRPEN_IN,
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output GT0_DRPRDY_OUT,
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input GT0_DRPWE_IN,
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//_________________________________________________________________________
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//_________________________________________________________________________
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//GT0 (X0Y4)
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//____________________________CHANNEL PORTS________________________________
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//----------------------- Channel - Ref Clock Ports ------------------------
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input GT0_GTREFCLK0_IN,
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//------------------------------ Channel PLL -------------------------------
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output GT0_CPLLFBCLKLOST_OUT,
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output GT0_CPLLLOCK_OUT,
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input GT0_CPLLLOCKDETCLK_IN,
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output GT0_CPLLREFCLKLOST_OUT,
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input GT0_CPLLRESET_IN,
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//----------------------------- Eye Scan Ports -----------------------------
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output GT0_EYESCANDATAERROR_OUT,
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//---------------------- Loopback and Powerdown Ports ----------------------
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input [2:0] GT0_LOOPBACK_IN,
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input [1:0] GT0_RXPD_IN,
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input [1:0] GT0_TXPD_IN,
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//----------------------------- Receive Ports ------------------------------
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input GT0_RXUSERRDY_IN,
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//--------------------- Receive Ports - 8b10b Decoder ----------------------
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output [1:0] GT0_RXCHARISCOMMA_OUT,
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output [1:0] GT0_RXCHARISK_OUT,
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output [1:0] GT0_RXDISPERR_OUT,
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output [1:0] GT0_RXNOTINTABLE_OUT,
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//----------------- Receive Ports - Clock Correction Ports -----------------
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output [1:0] GT0_RXCLKCORCNT_OUT,
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//------------- Receive Ports - Comma Detection and Alignment --------------
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input GT0_RXMCOMMAALIGNEN_IN,
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input GT0_RXPCOMMAALIGNEN_IN,
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//----------------- Receive Ports - RX Data Path interface -----------------
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input GT0_GTRXRESET_IN,
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output [15:0] GT0_RXDATA_OUT,
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output GT0_RXOUTCLK_OUT,
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input GT0_RXPCSRESET_IN,
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input GT0_RXPMARESET_IN,
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input GT0_RXUSRCLK_IN,
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input GT0_RXUSRCLK2_IN,
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//---------- Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
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input GT0_RXDFEAGCHOLD_IN,
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input GT0_RXDFELPMRESET_IN,
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output [6:0] GT0_RXMONITOROUT_OUT,
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input [1:0] GT0_RXMONITORSEL_IN,
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//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
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input GT0_GTXRXN_IN,
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input GT0_GTXRXP_IN,
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output GT0_RXCDRLOCK_OUT,
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//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
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input GT0_RXBUFRESET_IN,
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output [2:0] GT0_RXBUFSTATUS_OUT,
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//---------------------- Receive Ports - RX PLL Ports ----------------------
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output GT0_RXRESETDONE_OUT,
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//----------------------------- Transmit Ports -----------------------------
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input GT0_TXUSERRDY_IN,
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//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
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input [1:0] GT0_TXCHARDISPMODE_IN,
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input [1:0] GT0_TXCHARDISPVAL_IN,
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input [1:0] GT0_TXCHARISK_IN,
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//---------- Transmit Ports - TX Buffer and Phase Alignment Ports ----------
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output [1:0] GT0_TXBUFSTATUS_OUT,
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//---------------- Transmit Ports - TX Data Path interface -----------------
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input GT0_GTTXRESET_IN,
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input [15:0] GT0_TXDATA_IN,
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output GT0_TXOUTCLK_OUT,
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output GT0_TXOUTCLKFABRIC_OUT,
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output GT0_TXOUTCLKPCS_OUT,
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input GT0_TXPCSRESET_IN,
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input GT0_TXUSRCLK_IN,
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input GT0_TXUSRCLK2_IN,
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//-------------- Transmit Ports - TX Driver and OOB signaling --------------
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output GT0_GTXTXN_OUT,
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output GT0_GTXTXP_OUT,
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//--------------------- Transmit Ports - TX PLL Ports ----------------------
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output GT0_TXRESETDONE_OUT,
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//--------------- Transmit Ports - TX Ports for PCI Express ----------------
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input GT0_TXELECIDLE_IN,
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//____________________________COMMON PORTS________________________________
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//-------------------- Common Block - Ref Clock Ports ---------------------
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input GT0_GTREFCLK0_COMMON_IN,
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//----------------------- Common Block - QPLL Ports ------------------------
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output GT0_QPLLLOCK_OUT,
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input GT0_QPLLLOCKDETCLK_IN,
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output GT0_QPLLREFCLKLOST_OUT,
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input GT0_QPLLRESET_IN
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);
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//***************************** Parameter Declarations ************************
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parameter QPLL_FBDIV_TOP = 16;
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parameter QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 :
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(QPLL_FBDIV_TOP == 20) ? 10'b0000110000 :
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(QPLL_FBDIV_TOP == 32) ? 10'b0001100000 :
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(QPLL_FBDIV_TOP == 40) ? 10'b0010000000 :
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(QPLL_FBDIV_TOP == 64) ? 10'b0011100000 :
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(QPLL_FBDIV_TOP == 66) ? 10'b0101000000 :
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(QPLL_FBDIV_TOP == 80) ? 10'b0100100000 :
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(QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000;
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parameter QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 :
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(QPLL_FBDIV_TOP == 20) ? 1'b1 :
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(QPLL_FBDIV_TOP == 32) ? 1'b1 :
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(QPLL_FBDIV_TOP == 40) ? 1'b1 :
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(QPLL_FBDIV_TOP == 64) ? 1'b1 :
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(QPLL_FBDIV_TOP == 66) ? 1'b0 :
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(QPLL_FBDIV_TOP == 80) ? 1'b1 :
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(QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1;
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//***************************** Wire Declarations *****************************
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// ground and vcc signals
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wire tied_to_ground_i;
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wire [63:0] tied_to_ground_vec_i;
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wire tied_to_vcc_i;
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wire [63:0] tied_to_vcc_vec_i;
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wire gt0_qplloutclk_i;
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wire gt0_qplloutrefclk_i;
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wire gt0_qpllclk_i;
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wire gt0_qpllrefclk_i;
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//********************************* Main Body of Code**************************
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assign tied_to_ground_i = 1'b0;
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assign tied_to_ground_vec_i = 64'h0000000000000000;
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assign tied_to_vcc_i = 1'b1;
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assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
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assign gt0_qpllclk_i = gt0_qplloutclk_i;
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assign gt0_qpllrefclk_i = gt0_qplloutrefclk_i;
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//------------------------- GT Instances -------------------------------
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//_________________________________________________________________________
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//_________________________________________________________________________
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//GT0 (X0Y4)
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gige_sfp_mdio_GTWIZARD_GT #
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(
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// Simulation attributes
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.GT_SIM_GTRESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
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.SIM_VERSION (SIM_VERSION),
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.RX_DFE_KL_CFG2_IN (RX_DFE_KL_CFG2_IN),
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.PCS_RSVD_ATTR_IN (48'h000000000000),
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.PMA_RSV_IN (PMA_RSV_IN)
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)
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gt0_GTWIZARD_i
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(
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//-------------------------------- Channel ---------------------------------
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.QPLLCLK_IN (gt0_qpllclk_i),
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.QPLLREFCLK_IN (gt0_qpllrefclk_i),
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//-------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
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.DRPADDR_IN (GT0_DRPADDR_IN),
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.DRPCLK_IN (GT0_DRPCLK_IN),
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.DRPDI_IN (GT0_DRPDI_IN),
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.DRPDO_OUT (GT0_DRPDO_OUT),
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.DRPEN_IN (GT0_DRPEN_IN),
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.DRPRDY_OUT (GT0_DRPRDY_OUT),
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.DRPWE_IN (GT0_DRPWE_IN),
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//----------------------- Channel - Ref Clock Ports ------------------------
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.GTREFCLK0_IN (GT0_GTREFCLK0_IN),
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//------------------------------ Channel PLL -------------------------------
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.CPLLFBCLKLOST_OUT (GT0_CPLLFBCLKLOST_OUT),
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.CPLLLOCK_OUT (GT0_CPLLLOCK_OUT),
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.CPLLLOCKDETCLK_IN (GT0_CPLLLOCKDETCLK_IN),
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.CPLLREFCLKLOST_OUT (GT0_CPLLREFCLKLOST_OUT),
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.CPLLRESET_IN (GT0_CPLLRESET_IN),
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//----------------------------- Eye Scan Ports -----------------------------
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.EYESCANDATAERROR_OUT (GT0_EYESCANDATAERROR_OUT),
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//---------------------- Loopback and Powerdown Ports ----------------------
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.LOOPBACK_IN (GT0_LOOPBACK_IN),
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.RXPD_IN (GT0_RXPD_IN),
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.TXPD_IN (GT0_TXPD_IN),
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//----------------------------- Receive Ports ------------------------------
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.RXUSERRDY_IN (GT0_RXUSERRDY_IN),
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//--------------------- Receive Ports - 8b10b Decoder ----------------------
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.RXCHARISCOMMA_OUT (GT0_RXCHARISCOMMA_OUT),
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.RXCHARISK_OUT (GT0_RXCHARISK_OUT),
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.RXDISPERR_OUT (GT0_RXDISPERR_OUT),
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.RXNOTINTABLE_OUT (GT0_RXNOTINTABLE_OUT),
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//----------------- Receive Ports - Clock Correction Ports -----------------
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.RXCLKCORCNT_OUT (GT0_RXCLKCORCNT_OUT),
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//------------- Receive Ports - Comma Detection and Alignment --------------
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.RXMCOMMAALIGNEN_IN (GT0_RXMCOMMAALIGNEN_IN),
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.RXPCOMMAALIGNEN_IN (GT0_RXPCOMMAALIGNEN_IN),
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//----------------- Receive Ports - RX Data Path interface -----------------
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.GTRXRESET_IN (GT0_GTRXRESET_IN),
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.RXDATA_OUT (GT0_RXDATA_OUT),
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.RXOUTCLK_OUT (GT0_RXOUTCLK_OUT),
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.RXPCSRESET_IN (GT0_RXPCSRESET_IN),
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.RXPMARESET_IN (GT0_RXPMARESET_IN),
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.RXUSRCLK_IN (GT0_RXUSRCLK_IN),
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.RXUSRCLK2_IN (GT0_RXUSRCLK2_IN),
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//---------- Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
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.RXDFEAGCHOLD_IN (GT0_RXDFEAGCHOLD_IN),
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.RXDFELPMRESET_IN (GT0_RXDFELPMRESET_IN),
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.RXMONITOROUT_OUT (GT0_RXMONITOROUT_OUT),
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.RXMONITORSEL_IN (GT0_RXMONITORSEL_IN),
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//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
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.GTXRXN_IN (GT0_GTXRXN_IN),
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.GTXRXP_IN (GT0_GTXRXP_IN),
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.RXCDRLOCK_OUT (GT0_RXCDRLOCK_OUT),
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//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
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.RXBUFRESET_IN (GT0_RXBUFRESET_IN),
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.RXBUFSTATUS_OUT (GT0_RXBUFSTATUS_OUT),
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//---------------------- Receive Ports - RX PLL Ports ----------------------
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.RXRESETDONE_OUT (GT0_RXRESETDONE_OUT),
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//----------------------------- Transmit Ports -----------------------------
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.TXUSERRDY_IN (GT0_TXUSERRDY_IN),
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//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
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.TXCHARDISPMODE_IN (GT0_TXCHARDISPMODE_IN),
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.TXCHARDISPVAL_IN (GT0_TXCHARDISPVAL_IN),
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.TXCHARISK_IN (GT0_TXCHARISK_IN),
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//---------- Transmit Ports - TX Buffer and Phase Alignment Ports ----------
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.TXBUFSTATUS_OUT (GT0_TXBUFSTATUS_OUT),
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//---------------- Transmit Ports - TX Data Path interface -----------------
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.GTTXRESET_IN (GT0_GTTXRESET_IN),
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.TXDATA_IN (GT0_TXDATA_IN),
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.TXOUTCLK_OUT (GT0_TXOUTCLK_OUT),
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.TXOUTCLKFABRIC_OUT (GT0_TXOUTCLKFABRIC_OUT),
|
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.TXOUTCLKPCS_OUT (GT0_TXOUTCLKPCS_OUT),
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.TXPCSRESET_IN (GT0_TXPCSRESET_IN),
|
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.TXUSRCLK_IN (GT0_TXUSRCLK_IN),
|
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.TXUSRCLK2_IN (GT0_TXUSRCLK2_IN),
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//-------------- Transmit Ports - TX Driver and OOB signaling --------------
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.GTXTXN_OUT (GT0_GTXTXN_OUT),
|
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.GTXTXP_OUT (GT0_GTXTXP_OUT),
|
||||
//--------------------- Transmit Ports - TX PLL Ports ----------------------
|
||||
.TXRESETDONE_OUT (GT0_TXRESETDONE_OUT),
|
||||
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
|
||||
.TXELECIDLE_IN (GT0_TXELECIDLE_IN)
|
||||
|
||||
);
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||||
|
||||
|
||||
//_________________________________________________________________________
|
||||
//_________________________________________________________________________
|
||||
//_________________________GTXE2_COMMON____________________________________
|
||||
|
||||
GTXE2_COMMON #
|
||||
(
|
||||
// Simulation attributes
|
||||
.SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
|
||||
.SIM_QPLLREFCLK_SEL (3'b001),
|
||||
.SIM_VERSION (SIM_VERSION),
|
||||
|
||||
|
||||
//----------------COMMON BLOCK Attributes---------------
|
||||
.BIAS_CFG (64'h0000040000001000),
|
||||
.COMMON_CFG (32'h00000000),
|
||||
.QPLL_CFG (27'h06801C1),
|
||||
.QPLL_CLKOUT_CFG (4'b0000),
|
||||
.QPLL_COARSE_FREQ_OVRD (6'b010000),
|
||||
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
|
||||
.QPLL_CP (10'b0000011111),
|
||||
.QPLL_CP_MONITOR_EN (1'b0),
|
||||
.QPLL_DMONITOR_SEL (1'b0),
|
||||
.QPLL_FBDIV (QPLL_FBDIV_IN),
|
||||
.QPLL_FBDIV_MONITOR_EN (1'b0),
|
||||
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
|
||||
.QPLL_INIT_CFG (24'h000006),
|
||||
.QPLL_LOCK_CFG (16'h21E8),
|
||||
.QPLL_LPF (4'b1111),
|
||||
.QPLL_REFCLK_DIV (1)
|
||||
|
||||
)
|
||||
gtxe2_common_0_i
|
||||
(
|
||||
//----------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
|
||||
.DRPADDR (tied_to_ground_vec_i[7:0]),
|
||||
.DRPCLK (tied_to_ground_i),
|
||||
.DRPDI (tied_to_ground_vec_i[15:0]),
|
||||
.DRPDO (),
|
||||
.DRPEN (tied_to_ground_i),
|
||||
.DRPRDY (),
|
||||
.DRPWE (tied_to_ground_i),
|
||||
//-------------------- Common Block - Ref Clock Ports ---------------------
|
||||
.GTGREFCLK (tied_to_ground_i),
|
||||
.GTNORTHREFCLK0 (tied_to_ground_i),
|
||||
.GTNORTHREFCLK1 (tied_to_ground_i),
|
||||
.GTREFCLK0 (GT0_GTREFCLK0_COMMON_IN),
|
||||
.GTREFCLK1 (tied_to_ground_i),
|
||||
.GTSOUTHREFCLK0 (tied_to_ground_i),
|
||||
.GTSOUTHREFCLK1 (tied_to_ground_i),
|
||||
//----------------------- Common Block - QPLL Ports ------------------------
|
||||
.QPLLDMONITOR (),
|
||||
.QPLLFBCLKLOST (),
|
||||
.QPLLLOCK (GT0_QPLLLOCK_OUT),
|
||||
.QPLLLOCKDETCLK (GT0_QPLLLOCKDETCLK_IN),
|
||||
.QPLLLOCKEN (tied_to_vcc_i),
|
||||
.QPLLOUTCLK (gt0_qplloutclk_i),
|
||||
.QPLLOUTREFCLK (gt0_qplloutrefclk_i),
|
||||
.QPLLOUTRESET (tied_to_ground_i),
|
||||
.QPLLPD (tied_to_ground_i),
|
||||
.QPLLREFCLKLOST (GT0_QPLLREFCLKLOST_OUT),
|
||||
.QPLLREFCLKSEL (3'b001),
|
||||
.QPLLRESET (GT0_QPLLRESET_IN),
|
||||
.QPLLRSVD1 (16'b0000000000000000),
|
||||
.QPLLRSVD2 (5'b11111),
|
||||
.REFCLKOUTMONITOR (),
|
||||
//--------------------------- Common Block Ports ---------------------------
|
||||
.BGBYPASSB (tied_to_vcc_i),
|
||||
.BGMONITORENB (tied_to_vcc_i),
|
||||
.BGPDB (tied_to_vcc_i),
|
||||
.BGRCALOVRD (5'b00000),
|
||||
.PMARSVD (8'b00000000),
|
||||
.RCALENB (tied_to_vcc_i)
|
||||
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user