fpga: Multiple X300 FPGA bugfixes and enhancements

- Fixed 10GigE firmware communication issues and sequence errors for TX
- Multiple changes to help ease timing closure
- Cleaned up build scripts
- Switched to Xilinx ISE 14.7 as the default build tool for X300


Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0

top/x300/gige_phy/gige_sfp_mdio_reset_sync.v

@@ -0,0 +1,101 @@
+//------------------------------------------------------------------------------
+// File       : gige_sfp_mdio_reset_sync.v
+// Author     : Xilinx, Inc.
+//------------------------------------------------------------------------------
+// Description: Both flip-flops have the same asynchronous reset signal.
+//              Together the flops create a minimum of a 1 clock period
+//              duration pulse which is used for synchronous reset.
+//
+//              The flops are placed, using RLOCs, into the same slice.
+//------------------------------------------------------------------------------
+// (c) Copyright 2006-2008 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
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+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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+// including negligence, or under any other theory of
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+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
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+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
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+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES. 
+// 
+// 
+//------------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+module gige_sfp_mdio_reset_sync #(
+  parameter INITIALISE = 2'b11
+)
+(
+   input       reset_in,
+   input       clk,
+   output      reset_out
+);
+
+
+  (* shreg_extract = "no", ASYNC_REG = "TRUE" *)
+  wire  reset_stage1;
+
+  (* shreg_extract = "no", ASYNC_REG = "TRUE" *)
+  wire  reset_stage2;
+
+  FDP #(
+   .INIT (INITIALISE[0])
+  ) reset_sync1 (
+  .C  (clk), 
+  .PRE(reset_in),
+  .D  (1'b0),
+  .Q  (reset_stage1) 
+  );
+  
+  FDP #(
+   .INIT (INITIALISE[1])
+  ) reset_sync2 (
+  .C  (clk), 
+  .PRE(reset_in),
+  .D  (reset_stage1),
+  .Q  (reset_stage2) 
+  );
+
+
+assign reset_out = reset_stage2;
+
+
+
+endmodule