fpga: Multiple X300 FPGA bugfixes and enhancements
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
This commit is contained in:
Ashish Chaudhari
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//------------------------------------------------------------------------------
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// File : gige_sfp_mdio_block.v
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// Author : Xilinx Inc.
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//------------------------------------------------------------------------------
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// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//------------------------------------------------------------------------------
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// Description: This Core Block Level wrapper connects the core to a
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// Series-7 Transceiver.
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//
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//
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// ------------------------------------------------------------
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// | Core Block wrapper |
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// | |
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// | ------------------ ----------------- |
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// | | Core | | Transceiver | |
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// | | | | | |
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// | | | | | |
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// | | | | | |
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// ---------->| GMII |--------->| TXP |-------->
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// | | Tx | | TXN | |
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// | | | | | |
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// | | | | | |
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// | | | | | |
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// | | | | | |
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// | | | | | |
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// | | GMII | | RXP | |
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// <----------| Rx |<---------| RXN |<--------
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// | | | | | |
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// | ------------------ ----------------- |
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// | |
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// ------------------------------------------------------------
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//
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//
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`timescale 1 ps/1 ps
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//------------------------------------------------------------------------------
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// The module declaration for the Core Block wrapper.
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//------------------------------------------------------------------------------
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module gige_sfp_mdio_block
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(
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// Transceiver Interface
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//----------------------
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input gtrefclk, // Very high quality 125MHz clock for GT transceiver.
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output txp, // Differential +ve of serial transmission from PMA to PMD.
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output txn, // Differential -ve of serial transmission from PMA to PMD.
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input rxp, // Differential +ve for serial reception from PMD to PMA.
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input rxn, // Differential -ve for serial reception from PMD to PMA.
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output txoutclk, // txoutclk from GT transceiver (62.5MHz)
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output resetdone, // The GT transceiver has completed its reset cycle
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input mmcm_locked, // locked indication from MMCM
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input userclk, // 62.5MHz global clock.
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input userclk2, // 125MHz global clock.
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input independent_clock_bufg,// 200MHz Independent clock,
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input pma_reset, // transceiver PMA reset signal
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// GMII Interface
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//---------------
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input [7:0] gmii_txd, // Transmit data from client MAC.
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input gmii_tx_en, // Transmit control signal from client MAC.
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input gmii_tx_er, // Transmit control signal from client MAC.
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output [7:0] gmii_rxd, // Received Data to client MAC.
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output gmii_rx_dv, // Received control signal to client MAC.
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output gmii_rx_er, // Received control signal to client MAC.
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output gmii_isolate, // Tristate control to electrically isolate GMII.
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// Management: MDIO Interface
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//---------------------------
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input mdc, // Management Data Clock
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input mdio_i, // Management Data In
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output mdio_o, // Management Data Out
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output mdio_t, // Management Data Tristate
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input [4:0] phyad, // Port address for MDIO.
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input [4:0] configuration_vector, // Alternative to MDIO interface.
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input configuration_valid, // Validation signal for Config vector
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// General IO's
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//-------------
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output [15:0] status_vector, // Core status.
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input reset, // Asynchronous reset for entire core.
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input signal_detect // Input from PMD to indicate presence of optical input.
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);
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//---------------------------------------------------------------------------
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// Internal signals used in this block level wrapper.
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//---------------------------------------------------------------------------
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// Core <=> Transceiver interconnect
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wire plllock; // The PLL Locked status of the Transceiver
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wire mgt_rx_reset; // Reset for the receiver half of the Transceiver
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wire mgt_tx_reset; // Reset for the transmitter half of the Transceiver
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wire [1:0] rxbufstatus; // Elastic Buffer Status (bit 1 asserted indicates overflow or underflow).
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wire rxchariscomma; // Comma detected in RXDATA.
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wire rxcharisk; // K character received (or extra data bit) in RXDATA.
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wire [2:0] rxclkcorcnt; // Indicates clock correction.
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wire [7:0] rxdata; // Data after 8B/10B decoding.
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wire rxrundisp; // Running Disparity after current byte, becomes 9th data bit when RXNOTINTABLE='1'.
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wire rxdisperr; // Disparity-error in RXDATA.
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wire rxnotintable; // Non-existent 8B/10 code indicated.
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wire txbuferr; // TX Buffer error (overflow or underflow).
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wire loopback; // Set the Transceiver for loopback.
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wire powerdown; // Powerdown the Transceiver
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wire txchardispmode; // Set running disparity for current byte.
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wire txchardispval; // Set running disparity value.
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wire txcharisk; // K character transmitted in TXDATA.
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wire [7:0] txdata; // Data for 8B/10B encoding.
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wire enablealign; // Allow the transceivers to serially realign to a comma character.
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//---------------------------------------------------------------------------
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// Instantiate the core
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//---------------------------------------------------------------------------
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gige_sfp_mdio gig_eth_pcs_pma_core
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(
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.mgt_rx_reset (mgt_rx_reset),
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.mgt_tx_reset (mgt_tx_reset),
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.userclk (userclk2),
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.userclk2 (userclk2),
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.dcm_locked (mmcm_locked),
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.rxbufstatus (rxbufstatus),
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.rxchariscomma (rxchariscomma),
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.rxcharisk (rxcharisk),
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.rxclkcorcnt (rxclkcorcnt),
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.rxdata (rxdata),
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.rxdisperr (rxdisperr),
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.rxnotintable (rxnotintable),
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.rxrundisp (rxrundisp),
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.txbuferr (txbuferr),
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.powerdown (powerdown),
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.txchardispmode (txchardispmode),
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.txchardispval (txchardispval),
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.txcharisk (txcharisk),
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.txdata (txdata),
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.enablealign (enablealign),
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.gmii_txd (gmii_txd),
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.gmii_tx_en (gmii_tx_en),
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.gmii_tx_er (gmii_tx_er),
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.gmii_rxd (gmii_rxd),
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.gmii_rx_dv (gmii_rx_dv),
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.gmii_rx_er (gmii_rx_er),
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.gmii_isolate (gmii_isolate),
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.mdc (mdc),
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.mdio_in (mdio_i),
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.mdio_out (mdio_o),
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.mdio_tri (mdio_t),
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.phyad (phyad),
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.configuration_vector (configuration_vector),
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.configuration_valid (configuration_valid),
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.status_vector (status_vector),
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.reset (reset),
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.signal_detect (signal_detect)
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);
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//---------------------------------------------------------------------------
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// Component Instantiation for the Series-7 Transceiver wrapper
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//---------------------------------------------------------------------------
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gige_sfp_mdio_transceiver transceiver_inst (
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.encommaalign (enablealign),
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.loopback (loopback),
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.powerdown (powerdown),
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.usrclk (userclk),
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.usrclk2 (userclk2),
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.independent_clock (independent_clock_bufg),
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.data_valid (status_vector[1]),
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.txreset (mgt_tx_reset),
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.txchardispmode (txchardispmode),
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.txchardispval (txchardispval),
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.txcharisk (txcharisk),
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.txdata (txdata),
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.rxreset (mgt_rx_reset),
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.rxchariscomma (rxchariscomma),
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.rxcharisk (rxcharisk),
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.rxclkcorcnt (rxclkcorcnt),
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.rxdata (rxdata),
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.rxdisperr (rxdisperr),
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.rxnotintable (rxnotintable),
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.rxrundisp (rxrundisp),
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.rxbuferr (rxbufstatus[1]),
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.txbuferr (txbuferr),
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.plllkdet (plllock),
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.txoutclk (txoutclk),
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.txn (txn),
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.txp (txp),
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.rxn (rxn),
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.rxp (rxp),
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.gtrefclk (gtrefclk),
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.pmareset (pma_reset),
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.mmcm_locked (mmcm_locked),
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.resetdone (resetdone)
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);
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// Unused
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assign rxbufstatus[0] = 1'b0;
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// Loopback is performed in the core itself. To alternatively use
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// Transceiver loopback, please drive this port appropriately.
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assign loopback = 1'b0;
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endmodule // gige_sfp_mdio_block
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