fpga: Multiple X300 FPGA bugfixes and enhancements

- Fixed 10GigE firmware communication issues and sequence errors for TX
- Multiple changes to help ease timing closure
- Cleaned up build scripts
- Switched to Xilinx ISE 14.7 as the default build tool for X300


Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0

top/x300/gen_ddrlvds_tb.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ps
+`timescale 1ps/1ps
 
 module gen_ddrlvds_tb();
 
@@ -6,19 +6,16 @@ module gen_ddrlvds_tb();
    glbl glbl( );
 
    reg clk    = 1;
+   reg clk_2x = 1;
    reg reset  = 1;
-   reg tx_strobe = 0;
+   reg sync_dacs_req = 0;
    
    always #100 clk = ~clk;
-   always #200 tx_strobe = ~tx_strobe;
+   always #50 clk_2x = ~clk_2x;
    
-   
-   initial $dumpfile("gen_ddrlvds_tb.vcd");
-   initial $dumpvars(0,gen_ddrlvds_tb);
-
-   wire [7:0] pins_p, pins_n;
-   wire       frame_p, frame_n;
-   wire       clk_p, clk_n;
+   wire [7:0] dac_pins_p, dac_pins_n;
+   wire       dac_frame_p, dac_frame_n;
+   wire       dac_clk_p, dac_clk_n;
       
    reg [7:0]  count;
    
@@ -26,45 +23,49 @@ module gen_ddrlvds_tb();
    wire [15:0] q = {4'hB,count};
 
    initial
-     begin
-	#10000 reset = 0;
-	BURST(4);
-	BURST(5);
-	#2000;
-	$finish;
-     end
-   
+   begin
+      #500 reset = 0;
+		@(posedge clk);
+		//#10
+      sync_dacs_req <= 1;
+		#200
+      sync_dacs_req <= 0;
+		
+//      BURST (4);
+//      BURST (5);
+      #20000;
+   end
+
    task BURST;
       input [7:0] len;
-
+   begin
+      sync_dacs_req <= 0;
+      count <= 0;
+      @ (posedge clk);
+      @ (posedge clk);
+      repeat (len)
       begin
-//	 tx_strobe <= 0;
-	 count <= 0;
-	 @(posedge clk);
-	 @(posedge clk);
-	 repeat(len)
-	   begin
-	  //    tx_strobe <= 1;
-	      @(posedge clk);
-	  //    tx_strobe <= 0;
-	      @(posedge clk);
-	      count <= count + 1;
-	   end
-//	 tx_strobe <= 0;
-	 @(posedge clk);
-	 @(posedge clk);
-	 @(posedge clk);
+         sync_dacs_req <= 1;
+         @ (posedge clk);
+         sync_dacs_req <= 0;
+         @ (posedge clk);
+         count <= count + 1;
       end
-   endtask // BURST
-   
-   gen_ddrlvds gen_ddrlvds
-     (.rst(reset),
-      .tx_clk_p(clk_p), .tx_clk_n(clk_n),
-      .tx_frame_p(frame_p), .tx_frame_n(frame_n),
-      .tx_d_p(pins_p), .tx_d_n(pins_n),
-      .tx_clk(clk), .tx_strobe(tx_strobe),
-      .i(i), .q(q)
-      );
-   
-      
+      sync_dacs_req <= 0;
+      @ (posedge clk);
+      @ (posedge clk);
+      @ (posedge clk);
+   end
+   endtask //
+
+   gen_ddrlvds dut (
+      .reset(reset),
+      .tx_clk_2x_p(dac_clk_p), .tx_clk_2x_n(dac_clk_n),
+      .tx_frame_p(dac_frame_p), .tx_frame_n(dac_frame_n),
+      .tx_d_p(dac_pins_p), .tx_d_n(dac_pins_n),
+      .tx_clk_2x(clk_2x), .tx_clk_1x(clk),
+      .i(i), .q(q),
+      .sync_dacs(sync_dacs_req)
+   );
+
 endmodule // gen_ddrlvds_tb