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fpga: Multiple X300 FPGA bugfixes and enhancements

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- Fixed 10GigE firmware communication issues and sequence errors for TX
- Multiple changes to help ease timing closure
- Cleaned up build scripts
- Switched to Xilinx ISE 14.7 as the default build tool for X300


Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
This commit is contained in:
Ashish Chaudhari
2014-09-24 18:45:31 -07:00
parent 6b7004c311
commit adf2da6ac7
275 changed files with 14057 additions and 293393 deletions
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top/x300/Makefile
+21 -14
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@@ -28,15 +28,22 @@ clean:
print_report = \
echo "========================================================================"; \
cat $(1) | grep "Design Summary:" -A 124; \
cat $(1)/x300.syr | grep "Device utilization summary:" -A 30; \
echo "========================================================================"; \
echo "Timing Summary:\n"; \
cat $(1) | grep constraint | grep met | grep -v "*"; \
cat $(1)/x300.twr | grep constraint | grep met | grep -v "*"; \
echo "========================================================================";
# ise_build($1=Device, $2=Definitions)
ifndef EXPORT_ONLY
ise_build = make -f Makefile.x300.inc bin NAME=$@ DEVICE=$1 $2 EXTRA_DEFS="$2"
else
ise_build = @echo "Skipping ISE build and exporting pre-built files.";
endif
# post_build($1=Device, $2=Flavor)
post_build = \
@$(call print_report,build-$(1)_$(2)/build.log) \
@$(call print_report,build-$(1)_$(2)) \
mkdir -p build; \
echo "Exporting bitstream files..."; \
cp build-$(1)_$(2)/x300.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
@@ -45,54 +52,54 @@ post_build = \
$(CREATE_LVBITX) --input-bin=build-$(1)_$(2)/x300.bin --output-lvbitx=build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
cp -f x3x0_base.lvbitx build/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
echo "Exporting logs..."; \
cp build-$(1)_$(2)/build.log build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).log; \
cp build-$(1)_$(2)/x300.syr build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).syr; \
cp build-$(1)_$(2)/x300.twr build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).twr; \
echo "\nDONE ... $(1)_$(2)\n";
#1Gig on both ports
X310_1G:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(GIGE_DEFS) EXTRA_DEFS="$(GIGE_DEFS)"
$(call ise_build,XC7K410T,$(GIGE_DEFS))
$(call post_build,X310,1G)
X300_1G:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(GIGE_DEFS) EXTRA_DEFS="$(GIGE_DEFS)"
$(call ise_build,XC7K325T,$(GIGE_DEFS))
$(call post_build,X300,1G)
#1Gig on port0, 10Gig on port1
X310_HG:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)"
$(call ise_build,XC7K410T,$(HYBRID_DEFS))
$(call post_build,X310,HG)
X300_HG:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)"
$(call ise_build,XC7K325T,$(HYBRID_DEFS))
$(call post_build,X300,HG)
#10Gig on both ports
X310_XG:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)"
$(call ise_build,XC7K410T,$(XGIGE_DEFS))
$(call post_build,X310,XG)
X300_XG:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)"
$(call ise_build,XC7K325T,$(XGIGE_DEFS))
$(call post_build,X300,XG)
# 1Gig on port0, 10Gig on port1, SRAM Tx FIFO's
X310_HGS:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)"
$(call ise_build,XC7K410T,$(HYBRID_SRAM_DEFS))
$(call post_build,X310,HGS)
X300_HGS:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T FLOORPLAN=1 $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)"
$(call ise_build,XC7K325T,$(HYBRID_SRAM_DEFS))
$(call post_build,X300,HGS)
# 10Gig on both ports, SRAM Tx FIFO's
X310_XGS:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)"
$(call ise_build,XC7K410T,$(XGIGE_SRAM_DEFS))
$(call post_build,X310,XGS)
X300_XGS:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)"
$(call ise_build,XC7K325T,$(XGIGE_SRAM_DEFS))
$(call post_build,X300,XGS)