miegl/b210-k7-fpga
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fpga: Multiple X300 FPGA bugfixes and enhancements

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- Fixed 10GigE firmware communication issues and sequence errors for TX
- Multiple changes to help ease timing closure
- Cleaned up build scripts
- Switched to Xilinx ISE 14.7 as the default build tool for X300


Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
This commit is contained in:
Ashish Chaudhari
2014-09-24 18:45:31 -07:00
parent 6b7004c311
commit adf2da6ac7
275 changed files with 14057 additions and 293393 deletions
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lib/xge_interface/xge_mac_wrapper.v
+3 -3
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@@ -151,7 +151,7 @@ module xge_mac_wrapper
///////////////////////////////////////////////////////////////////////////////////////
wire [63:0] rx_tdata_int;
wire [3:0] rx_tuser_int;
wire rx_talst_int;
wire rx_tlast_int;
wire rx_tvalid_int;
wire rx_tready_int;
@@ -194,7 +194,7 @@ module xge_mac_wrapper
// Large FIFO must be able to run input side at 64b@156MHz to sustain 10Gb Rx.
//
axi64_8k_2clk_fifo rxfifo_2clk
axi64_4k_2clk_fifo rxfifo_2clk
(
.s_aresetn(~xgmii_reset),
.s_aclk(xgmii_clk),
@@ -235,7 +235,7 @@ module xge_mac_wrapper
wire tx_sof_int3;
axi64_8k_2clk_fifo txfifo_2clk_1x
axi64_4k_2clk_fifo txfifo_2clk_1x
(
.s_aresetn(~xgmii_reset),
.s_aclk(sys_clk),