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fpga: tools: Add support for RFSoC

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This commit includes the following changes to the tools:
- Change part definition in XCI and BD editors for the RFSoC family
- Resolve part name in Vivado IP management utilities with
  viv_gen_part_id.py


Original-commit: fba23eb42c91ca1bc1108b5ba50c1b567cb9b59d
This commit is contained in:
Humberto Jimenez
2021-06-03 10:22:04 -05:00
committed by Aaron Rossetto
parent 7ec0561c4d
commit ad6b7bdee8
2 changed files with 9 additions and 9 deletions
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tools/scripts/viv_ip_xci_editor.py
+5 -1
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@@ -57,7 +57,11 @@ def main():
if args.action == 'read_partid':
print(xci_info['DEVICE'] + '/' + xci_info['PACKAGE'] + '/' + xci_info['SPEEDGRADE'] + '/' + xci_info['TEMPERATURE_GRADE'] + '/' + xci_info['SILICON_REVISION'])
if args.action == 'read_part':
print(xci_info['DEVICE'] + xci_info['PACKAGE'] + xci_info['SPEEDGRADE'])
# The UltraScale+ RFSoC family ids are expected diferently in Vivado, a '-' must separate each property.
if xci_info['ARCHITECTURE'] == "zynquplusRFSOC":
print(xci_info['DEVICE'] + "-" + xci_info['PACKAGE'] + xci_info['SPEEDGRADE'] + "-" + xci_info['TEMPERATURE_GRADE'])
else:
print(xci_info['DEVICE'] + xci_info['PACKAGE'] + xci_info['SPEEDGRADE'])
elif args.action == 'retarget':
# Write a new XCI file with modified target info
if not os.path.isdir(args.output_dir):