fpga: lib: Add clock_div module

Module description: Clock divider. Generates an output clock that is 1/N times the frequency of the input clock. Original-commit: 71bdcd22f07162687771d374178ad0372783bd45
2023-04-05 15:10:14 -05:00
parent cd3b980e25
commit a90444c784
2 changed files with 54 additions and 0 deletions
@@ -20,6 +20,7 @@ axi_slave_mux.v \
 axi_test_vfifo.v \
 bin2gray.v \
 binary_encoder.v \
+clock_div.v \
 db_control.v \
 fe_control.v \
 filter_bad_sid.v \