fpga: Add Vivado project option to USRP FPGA builds

Original-commit: 2e0db35eaf69947c344f67c9f38132e33f88a141
2024-03-15 20:05:39 -05:00
parent 51865aa003
commit a82a2d122e
5 changed files with 5 additions and 0 deletions
@@ -112,6 +112,7 @@ help:           ##Show this help message.
 ##DRAM=1         Include DDR3 SDRAM memory controller IP in the FPGA build.
 ##               Note: The RFNoC image core must also be configured to use DRAM.
 ##GUI=1          Launch the build in the Vivado GUI.
+##PROJECT=1      Save Vivado project file, otherwise it's created in memory.
 ##CHECK=1        Launch the syntax checker instead of building a bitfile.
 ##SYNTH=1        Launch the build but stop after synthesis.
 ##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)