miegl/b210-k7-fpga
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fpga: lib: Upgrade to Vivado 2021.1

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Original-commit: b0dc0faed1eceef3ba28ce03555658fca2423c46
This commit is contained in:
Sam O'Brien authored and skooNI committed 2022-08-25 13:55:30 -05:00
1 parent f53e3f27fc
commit a63c80bd23
24 files changed
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lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/Makefile
+1 -1
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@@ -54,7 +54,7 @@ $(IP_FIFO_SHORT_2CLK_SRCS) \
include $(BASE_DIR)/../sim/general/Makefile.srcs
include $(BASE_DIR)/../sim/axi/Makefile.srcs
MODELSIM_LIBS += unisims_ver secureip fifo_generator_v13_2_4
MODELSIM_LIBS += unisims_ver secureip fifo_generator_v13_2_5
# Define only one top-level module
SIM_TOP = cat_io_lvds_dual_mode_tb glbl