From a63c80bd23070975c8c27c1992518d028253fdd3 Mon Sep 17 00:00:00 2001 From: Sam O'Brien Date: Wed, 2 Feb 2022 09:10:04 -0600 Subject: [PATCH] fpga: lib: Upgrade to Vivado 2021.1 Original-commit: b0dc0faed1eceef3ba28ce03555658fca2423c46 --- lib/axi4s_sv/axi4s_add_bytes.sv | 10 +-- lib/hls/addsub_hls/addsub_hls.cpp | 64 +++++++++++-------- lib/ip/axi_fft/axi_fft.xci | 39 ++++++++--- lib/ip/axi_hb31/axi_hb31.xci | 47 +++++++++++--- lib/ip/axi_hb47/axi_hb47.xci | 47 +++++++++++--- .../complex_multiplier/complex_multiplier.xci | 37 ++++++++--- .../complex_multiplier_dds.xci | 33 +++++++--- .../complex_to_magphase.xci | 27 ++++++-- .../complex_to_magphase_int16_int24.xci | 27 ++++++-- .../complex_to_magphase_int32.xci | 27 ++++++-- .../cordic_rotate_int24.xci | 31 +++++++-- .../cordic_rotate_int24_int16.xci | 31 +++++++-- lib/ip/cordic_rotator/cordic_rotator.xci | 31 +++++++-- lib/ip/cordic_rotator24/cordic_rotator24.xci | 31 +++++++-- lib/ip/dds/dds.xci | 38 ++++++++--- .../dds_sin_cos_lut_only.xci | 35 +++++++--- lib/ip/divide_int16/divide_int16.xci | 31 +++++++-- .../divide_int16_int32/divide_int16_int32.xci | 31 +++++++-- lib/ip/divide_int24/divide_int24.xci | 31 +++++++-- lib/ip/divide_int32/divide_int32.xci | 31 +++++++-- lib/ip/divide_uint32/divide_uint32.xci | 31 +++++++-- .../rfnoc_block_addsub_tb.sv | 2 +- lib/rfnoc/xport_sv/eth_interface_tb/Makefile | 6 +- .../cat_io_lvds_dual_mode_tb/Makefile | 2 +- 24 files changed, 543 insertions(+), 177 deletions(-) diff --git a/lib/axi4s_sv/axi4s_add_bytes.sv b/lib/axi4s_sv/axi4s_add_bytes.sv index cb56a68..7c2169e 100644 --- a/lib/axi4s_sv/axi4s_add_bytes.sv +++ b/lib/axi4s_sv/axi4s_add_bytes.sv @@ -83,11 +83,11 @@ module axi4s_add_bytes #( logic reached_start; logic reached_end; logic byte_overflow; - logic [s0.DATA_WIDTH-1:0] zero_data; - logic [s0.DATA_WIDTH-1:0] last_tdata; - logic [s0.DATA_WIDTH-1:0] remaining_shift_data; - logic [s0.DATA_WIDTH-1:0] last_shift_data; - logic [s0.DATA_WIDTH-1:0] first_shifted_data; + logic [i.DATA_WIDTH-1:0] zero_data; + logic [i.DATA_WIDTH-1:0] last_tdata; + logic [i.DATA_WIDTH-1:0] remaining_shift_data; + logic [i.DATA_WIDTH-1:0] last_shift_data; + logic [i.DATA_WIDTH-1:0] first_shifted_data; logic error_bit, error_bit_old; diff --git a/lib/hls/addsub_hls/addsub_hls.cpp b/lib/hls/addsub_hls/addsub_hls.cpp index 1cb27c1..1d9d7ea 100644 --- a/lib/hls/addsub_hls/addsub_hls.cpp +++ b/lib/hls/addsub_hls/addsub_hls.cpp @@ -1,41 +1,51 @@ // -// Copyright 2016 Ettus Research, a National Instruments Company +// Copyright 2022 Ettus Research, a National Instruments Company // // SPDX-License-Identifier: LGPL-3.0-or-later // +#include "ap_axi_sdata.h" +#include "hls_stream.h" #include -#include "ap_int.h" -struct axis_cplx { - std::complex data; - ap_uint<1> last; -}; +typedef std::complex axis_data; +typedef hls::axis trans_pkt; // AXI-Stream port type is compatible with pointer, reference, & array input / ouputs only // See UG902 Vivado High Level Synthesis guide (2014.4) pg 157 Figure 1-49 -void addsub_hls (axis_cplx &a, axis_cplx &b, axis_cplx &add, axis_cplx &sub) { +void addsub_hls(hls::stream& a, + hls::stream& b, + hls::stream& add, + hls::stream& sub) +{ + // Remove ap ctrl ports (ap_start, ap_ready, ap_idle, etc) since we only use the + // AXI-Stream ports + #pragma HLS INTERFACE ap_ctrl_none port = return - // Remove ap ctrl ports (ap_start, ap_ready, ap_idle, etc) since we only use the AXI-Stream ports - #pragma HLS INTERFACE ap_ctrl_none port=return - // Set ports as AXI-Stream - #pragma HLS INTERFACE axis port=sub - #pragma HLS INTERFACE axis port=add - #pragma HLS INTERFACE axis port=a - #pragma HLS INTERFACE axis port=b - // Need to pack our complex into a 32-bit word - // Otherwise, compiler complains that our AXI-Stream interfaces have two data fields (i.e. data.real, data.imag) - #pragma HLS DATA_PACK variable=sub.data - #pragma HLS DATA_PACK variable=add.data - #pragma HLS DATA_PACK variable=a.data - #pragma HLS DATA_PACK variable=b.data + // Set ports as AXI-Stream + #pragma HLS INTERFACE axis port = sub + #pragma HLS INTERFACE axis port = add + #pragma HLS INTERFACE axis port = a + #pragma HLS INTERFACE axis port = b // Complex add / subtract - add.data.real() = a.data.real() + b.data.real(); - add.data.imag() = a.data.imag() + b.data.imag(); - sub.data.real() = a.data.real() - b.data.real(); - sub.data.imag() = a.data.imag() - b.data.imag(); - // Pass through tlast - add.last = a.last; - sub.last = a.last; + trans_pkt a_pkt; + a.read(a_pkt); + + trans_pkt b_pkt; + b.read(b_pkt); + + trans_pkt add_pkt; + add_pkt.data = { + a_pkt.data.real() + b_pkt.data.real(), + a_pkt.data.imag() + b_pkt.data.imag()}; + add_pkt.last = a_pkt.last; + add.write(add_pkt); + + trans_pkt sub_pkt; + sub_pkt.data = { + a_pkt.data.real() - b_pkt.data.real(), + a_pkt.data.imag() - b_pkt.data.imag()}; + sub_pkt.last = a_pkt.last; + sub.write(sub_pkt); } diff --git a/lib/ip/axi_fft/axi_fft.xci b/lib/ip/axi_fft/axi_fft.xci index a33d900..07455c5 100644 --- a/lib/ip/axi_fft/axi_fft.xci +++ b/lib/ip/axi_fft/axi_fft.xci @@ -9,11 +9,11 @@ axi_fft - ACTIVE_LOW 100000000 + 0 0 - 0.000 + 0.0 0 1 1 @@ -30,7 +30,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -43,7 +43,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -56,7 +56,7 @@ 0 0 undef - 0.000 + 0.0 3 0 0 @@ -69,7 +69,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -98,6 +98,7 @@ 10 0 16 + xc7k410tffg900-2 1 24 32 @@ -147,12 +148,12 @@ TRUE TRUE IP_Flow - 2 + 6 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -200,6 +201,28 @@ + + + diff --git a/lib/ip/axi_hb31/axi_hb31.xci b/lib/ip/axi_hb31/axi_hb31.xci index 3af4dba..f259666 100644 --- a/lib/ip/axi_hb31/axi_hb31.xci +++ b/lib/ip/axi_hb31/axi_hb31.xci @@ -9,11 +9,11 @@ axi_hb31 - ACTIVE_LOW 100000000 + 0 0 - 0.000 + 0.0 0 1 1 @@ -30,7 +30,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -43,7 +43,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -56,7 +56,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -69,7 +69,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -151,6 +151,7 @@ Vector -581, 0, 1053, -0, -1759, 0, 2814, -0, -4434, 0, 7193, -0, -13190, 0, 41478, 65536, 41478, 0, -13190, -0, 7193, 0, -4434, -0, 2814, 0, -1759, -0, 1053, 0, -581 Automatic + false no_coe_file_loaded 0 false @@ -160,13 +161,20 @@ 18 8 axi_hb31 + false + false + false + false Not_Required 1 Automatic 0 + false + false Signed 16 1 + false false Systolic_Multiply_Accumulate 1 @@ -184,18 +192,23 @@ true Not_Required Automatic + false + false 1 1 2 + false Area None None + false Automatic Truncate_LSBs 16 0.5 0.0 P4-0,P4-1,P4-2,P4-3,P4-4 + false Automatic Integer_Coefficients Frequency_Specification @@ -226,12 +239,12 @@ TRUE TRUE IP_Flow - 12 + 16 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -300,6 +313,24 @@ + + + diff --git a/lib/ip/axi_hb47/axi_hb47.xci b/lib/ip/axi_hb47/axi_hb47.xci index 749a3f9..7d9c58e 100644 --- a/lib/ip/axi_hb47/axi_hb47.xci +++ b/lib/ip/axi_hb47/axi_hb47.xci @@ -9,11 +9,11 @@ axi_hb47 - ACTIVE_LOW 100000000 + 0 0 - 0.000 + 0.0 0 1 1 @@ -30,7 +30,7 @@ 0 0 undef - 0.000 + 0.0 6 0 0 @@ -43,7 +43,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -56,7 +56,7 @@ 0 0 undef - 0.000 + 0.0 6 0 0 @@ -69,7 +69,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -151,6 +151,7 @@ Vector -62, 0, 194, 0, -440, 0, 855, 0, -1505, 0, 2478, 0, -3900, 0, 5990, 0, -9187, 0, 14632, 0, -26536, 0, 83009, 131071, 83009, 0, -26536, 0, 14632, 0, -9187, 0, 5990, 0, -3900, 0, 2478, 0, -1505, 0, 855, 0, -440, 0, 194, 0, -62 Automatic + false no_coe_file_loaded 0 false @@ -160,13 +161,20 @@ 18 6 axi_hb47 + false + false + false + false Not_Required 1 Automatic 0 + false + false Signed 24 1 + false false Systolic_Multiply_Accumulate 1 @@ -184,18 +192,23 @@ true Not_Required Automatic + false + false 1 1 2 + false Area None None + false Automatic Non_Symmetric_Rounding_Up 24 0.5 0.0 P4-0,P4-1,P4-2,P4-3,P4-4 + false Automatic Integer_Coefficients Frequency_Specification @@ -226,12 +239,12 @@ TRUE TRUE IP_Flow - 12 + 16 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -290,6 +303,24 @@ + + + diff --git a/lib/ip/complex_multiplier/complex_multiplier.xci b/lib/ip/complex_multiplier/complex_multiplier.xci index 48966fa..d57bdfc 100644 --- a/lib/ip/complex_multiplier/complex_multiplier.xci +++ b/lib/ip/complex_multiplier/complex_multiplier.xci @@ -9,11 +9,11 @@ complex_multiplier - ACTIVE_LOW 10000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 8 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -62,7 +62,7 @@ 0 0 undef - 0.000 + 0.0 1 0 0 @@ -134,12 +134,12 @@ TRUE TRUE IP_Flow - 17 + 20 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -177,6 +177,27 @@ + + + diff --git a/lib/ip/complex_multiplier_dds/complex_multiplier_dds.xci b/lib/ip/complex_multiplier_dds/complex_multiplier_dds.xci index 13a739a..a2e26ea 100644 --- a/lib/ip/complex_multiplier_dds/complex_multiplier_dds.xci +++ b/lib/ip/complex_multiplier_dds/complex_multiplier_dds.xci @@ -9,11 +9,11 @@ complex_multiplier_dds - ACTIVE_LOW 10000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 8 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 6 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -62,7 +62,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -134,12 +134,12 @@ TRUE TRUE IP_Flow - 17 + 20 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -181,6 +181,23 @@ + + + diff --git a/lib/ip/complex_to_magphase/complex_to_magphase.xci b/lib/ip/complex_to_magphase/complex_to_magphase.xci index 825bf67..d314f45 100644 --- a/lib/ip/complex_to_magphase/complex_to_magphase.xci +++ b/lib/ip/complex_to_magphase/complex_to_magphase.xci @@ -9,11 +9,11 @@ complex_to_magphase - ACTIVE_LOW 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -123,12 +123,12 @@ TRUE TRUE IP_Flow - 15 + 17 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -162,6 +162,19 @@ + + + diff --git a/lib/ip/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci b/lib/ip/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci index fb19e47..3849c1e 100644 --- a/lib/ip/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci +++ b/lib/ip/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci @@ -9,11 +9,11 @@ complex_to_magphase_int16_int24 - ACTIVE_LOW 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 6 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -123,12 +123,12 @@ TRUE TRUE IP_Flow - 15 + 17 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -164,6 +164,19 @@ + + + diff --git a/lib/ip/complex_to_magphase_int32/complex_to_magphase_int32.xci b/lib/ip/complex_to_magphase_int32/complex_to_magphase_int32.xci index a9c9631..8840e96 100644 --- a/lib/ip/complex_to_magphase_int32/complex_to_magphase_int32.xci +++ b/lib/ip/complex_to_magphase_int32/complex_to_magphase_int32.xci @@ -9,11 +9,11 @@ complex_to_magphase_int32 - ACTIVE_LOW 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 8 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 8 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -123,12 +123,12 @@ TRUE TRUE IP_Flow - 15 + 17 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -164,6 +164,19 @@ + + + diff --git a/lib/ip/cordic_rotate_int24/cordic_rotate_int24.xci b/lib/ip/cordic_rotate_int24/cordic_rotate_int24.xci index 2e1f47f..d9635aa 100644 --- a/lib/ip/cordic_rotate_int24/cordic_rotate_int24.xci +++ b/lib/ip/cordic_rotate_int24/cordic_rotate_int24.xci @@ -9,11 +9,11 @@ cordic_rotate_int24 - ACTIVE_LOW 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 6 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 6 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 3 0 0 @@ -123,12 +123,12 @@ TRUE TRUE IP_Flow - 15 + 17 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -164,6 +164,23 @@ + + + diff --git a/lib/ip/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci b/lib/ip/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci index 46d5fee..fe6228e 100644 --- a/lib/ip/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci +++ b/lib/ip/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci @@ -9,11 +9,11 @@ cordic_rotate_int24_int16 - ACTIVE_LOW 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 6 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 3 0 0 @@ -123,12 +123,12 @@ TRUE TRUE IP_Flow - 15 + 17 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -163,6 +163,23 @@ + + + diff --git a/lib/ip/cordic_rotator/cordic_rotator.xci b/lib/ip/cordic_rotator/cordic_rotator.xci index 63b7aaf..fafef46 100644 --- a/lib/ip/cordic_rotator/cordic_rotator.xci +++ b/lib/ip/cordic_rotator/cordic_rotator.xci @@ -9,11 +9,11 @@ cordic_rotator - ACTIVE_LOW 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 2 0 0 @@ -123,12 +123,12 @@ TRUE TRUE IP_Flow - 15 + 17 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -159,6 +159,23 @@ + + + diff --git a/lib/ip/cordic_rotator24/cordic_rotator24.xci b/lib/ip/cordic_rotator24/cordic_rotator24.xci index 970220f..a7ae519 100644 --- a/lib/ip/cordic_rotator24/cordic_rotator24.xci +++ b/lib/ip/cordic_rotator24/cordic_rotator24.xci @@ -9,11 +9,11 @@ cordic_rotator24 - ACTIVE_LOW 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 6 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 6 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 3 0 0 @@ -123,12 +123,12 @@ TRUE TRUE IP_Flow - 15 + 17 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -162,6 +162,23 @@ + + + diff --git a/lib/ip/dds/dds.xci b/lib/ip/dds/dds.xci index 0af68af..60a1cce 100644 --- a/lib/ip/dds/dds.xci +++ b/lib/ip/dds/dds.xci @@ -9,11 +9,11 @@ dds - ACTIVE_LOW 100000000 + 0 0 - 0.000 + 0.0 0 1 1 @@ -31,7 +31,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -44,7 +44,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -57,7 +57,7 @@ 0 0 undef - 0.000 + 0.0 8 0 0 @@ -70,7 +70,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -239,12 +239,12 @@ TRUE TRUE IP_Flow - 18 + 21 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -298,6 +298,28 @@ + + + diff --git a/lib/ip/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci b/lib/ip/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci index 0efbb69..82e716a 100644 --- a/lib/ip/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci +++ b/lib/ip/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci @@ -9,11 +9,11 @@ dds_sin_cos_lut_only - ACTIVE_LOW 100000000 + 0 0 - 0.000 + 0.0 0 1 1 @@ -31,7 +31,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -44,7 +44,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -57,7 +57,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -70,7 +70,7 @@ 0 0 undef - 0.000 + 0.0 3 0 0 @@ -239,12 +239,12 @@ TRUE TRUE IP_Flow - 18 + 21 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -304,6 +304,25 @@ + + + diff --git a/lib/ip/divide_int16/divide_int16.xci b/lib/ip/divide_int16/divide_int16.xci index b052c06..c48ab14 100644 --- a/lib/ip/divide_int16/divide_int16.xci +++ b/lib/ip/divide_int16/divide_int16.xci @@ -9,11 +9,11 @@ divide_int16 - ACTIVE_LOW 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 2 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 2 0 0 @@ -115,12 +115,12 @@ TRUE TRUE IP_Flow - 15 + 18 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -155,6 +155,23 @@ + + + diff --git a/lib/ip/divide_int16_int32/divide_int16_int32.xci b/lib/ip/divide_int16_int32/divide_int16_int32.xci index fb85b0f..3b90e58 100644 --- a/lib/ip/divide_int16_int32/divide_int16_int32.xci +++ b/lib/ip/divide_int16_int32/divide_int16_int32.xci @@ -9,11 +9,11 @@ divide_int16_int32 - ACTIVE_LOW 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 6 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 2 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -115,12 +115,12 @@ TRUE TRUE IP_Flow - 15 + 18 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -157,6 +157,23 @@ + + + diff --git a/lib/ip/divide_int24/divide_int24.xci b/lib/ip/divide_int24/divide_int24.xci index d98c735..50d90dd 100644 --- a/lib/ip/divide_int24/divide_int24.xci +++ b/lib/ip/divide_int24/divide_int24.xci @@ -9,11 +9,11 @@ divide_int24 - ACTIVE_LOW 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 6 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 3 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 3 0 0 @@ -115,12 +115,12 @@ TRUE TRUE IP_Flow - 15 + 18 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -158,6 +158,23 @@ + + + diff --git a/lib/ip/divide_int32/divide_int32.xci b/lib/ip/divide_int32/divide_int32.xci index b57c10a..0019f33 100644 --- a/lib/ip/divide_int32/divide_int32.xci +++ b/lib/ip/divide_int32/divide_int32.xci @@ -9,11 +9,11 @@ divide_int32 - ACTIVE_LOW 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 8 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -115,12 +115,12 @@ TRUE TRUE IP_Flow - 15 + 18 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -158,6 +158,23 @@ + + + diff --git a/lib/ip/divide_uint32/divide_uint32.xci b/lib/ip/divide_uint32/divide_uint32.xci index 12d19d7..5a68efd 100644 --- a/lib/ip/divide_uint32/divide_uint32.xci +++ b/lib/ip/divide_uint32/divide_uint32.xci @@ -9,11 +9,11 @@ divide_uint32 - ACTIVE_LOW 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -23,7 +23,7 @@ 0 0 undef - 0.000 + 0.0 8 0 0 @@ -36,7 +36,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -49,7 +49,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -115,12 +115,12 @@ TRUE TRUE IP_Flow - 15 + 18 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -159,6 +159,23 @@ + + + diff --git a/lib/rfnoc/blocks/rfnoc_block_addsub/rfnoc_block_addsub_tb.sv b/lib/rfnoc/blocks/rfnoc_block_addsub/rfnoc_block_addsub_tb.sv index 10e9f96..9af91a2 100644 --- a/lib/rfnoc/blocks/rfnoc_block_addsub/rfnoc_block_addsub_tb.sv +++ b/lib/rfnoc/blocks/rfnoc_block_addsub/rfnoc_block_addsub_tb.sv @@ -17,7 +17,7 @@ module rfnoc_block_addsub_tb #( - parameter string USE_IMPL = "Verilog" + parameter USE_IMPL = "Verilog" ); `include "test_exec.svh" diff --git a/lib/rfnoc/xport_sv/eth_interface_tb/Makefile b/lib/rfnoc/xport_sv/eth_interface_tb/Makefile index d40b6f3..c8ded69 100644 --- a/lib/rfnoc/xport_sv/eth_interface_tb/Makefile +++ b/lib/rfnoc/xport_sv/eth_interface_tb/Makefile @@ -52,7 +52,7 @@ $(IP_FIFO_SHORT_2CLK_SRCS) \ #------------------------------------------------- # Testbench Specific #------------------------------------------------- -MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_4 +MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_5 MODELSIM_ARGS += glbl -t 1fs # Define toplevel module TB_TOP_MODULE ?= eth_ifc_all_tb @@ -68,8 +68,8 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \ # Suppressing the following worthless reminder. #* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] - # Extra checking for conflicts with always_comb and always_latch variables is done at vopt time -SVLOG_ARGS = -suppress 2583 -keep_delta -VLOG_ARGS = -keep_delta +SVLOG_ARGS = -suppress 2583 -keep_delta +VLOG_ARGS = -keep_delta #------------------------------------------------- # Bottom-of-Makefile diff --git a/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/Makefile b/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/Makefile index 20795a9..3d795ed 100644 --- a/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/Makefile +++ b/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/Makefile @@ -54,7 +54,7 @@ $(IP_FIFO_SHORT_2CLK_SRCS) \ include $(BASE_DIR)/../sim/general/Makefile.srcs include $(BASE_DIR)/../sim/axi/Makefile.srcs -MODELSIM_LIBS += unisims_ver secureip fifo_generator_v13_2_4 +MODELSIM_LIBS += unisims_ver secureip fifo_generator_v13_2_5 # Define only one top-level module SIM_TOP = cat_io_lvds_dual_mode_tb glbl