fpga: lib: Upgrade to Vivado 2021.1

Original-commit: b0dc0faed1eceef3ba28ce03555658fca2423c46
2022-08-25 13:55:30 -05:00
parent f53e3f27fc
commit a63c80bd23
24 changed files with 543 additions and 177 deletions
@@ -17,7 +17,7 @@


 module rfnoc_block_addsub_tb #(
-  parameter string USE_IMPL = "Verilog"
+  parameter USE_IMPL = "Verilog"
 );

  `include "test_exec.svh"