fpga: lib: Upgrade to Vivado 2021.1

Original-commit: b0dc0faed1eceef3ba28ce03555658fca2423c46
This commit is contained in:
Sam O'Brien
2022-08-25 13:55:30 -05:00
committed by skooNI
parent f53e3f27fc
commit a63c80bd23
24 changed files with 543 additions and 177 deletions
@@ -17,7 +17,7 @@
module rfnoc_block_addsub_tb #(
parameter string USE_IMPL = "Verilog"
parameter USE_IMPL = "Verilog"
);
`include "test_exec.svh"
+3 -3
View File
@@ -52,7 +52,7 @@ $(IP_FIFO_SHORT_2CLK_SRCS) \
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_4
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_5
MODELSIM_ARGS += glbl -t 1fs
# Define toplevel module
TB_TOP_MODULE ?= eth_ifc_all_tb
@@ -68,8 +68,8 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
# Suppressing the following worthless reminder.
#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
SVLOG_ARGS = -suppress 2583 -keep_delta
VLOG_ARGS = -keep_delta
SVLOG_ARGS = -suppress 2583 -keep_delta
VLOG_ARGS = -keep_delta
#-------------------------------------------------
# Bottom-of-Makefile