fpga: lib: Upgrade to Vivado 2021.1
Original-commit: b0dc0faed1eceef3ba28ce03555658fca2423c46
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@@ -1,41 +1,51 @@
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//
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// Copyright 2016 Ettus Research, a National Instruments Company
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// Copyright 2022 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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#include "ap_axi_sdata.h"
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#include "hls_stream.h"
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#include <complex>
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#include "ap_int.h"
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struct axis_cplx {
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std::complex<short int> data;
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ap_uint<1> last;
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};
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typedef std::complex<short int> axis_data;
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typedef hls::axis<axis_data, 0, 0, 0> trans_pkt;
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// AXI-Stream port type is compatible with pointer, reference, & array input / ouputs only
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// See UG902 Vivado High Level Synthesis guide (2014.4) pg 157 Figure 1-49
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void addsub_hls (axis_cplx &a, axis_cplx &b, axis_cplx &add, axis_cplx &sub) {
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void addsub_hls(hls::stream<trans_pkt>& a,
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hls::stream<trans_pkt>& b,
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hls::stream<trans_pkt>& add,
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hls::stream<trans_pkt>& sub)
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{
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// Remove ap ctrl ports (ap_start, ap_ready, ap_idle, etc) since we only use the
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// AXI-Stream ports
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#pragma HLS INTERFACE ap_ctrl_none port = return
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// Remove ap ctrl ports (ap_start, ap_ready, ap_idle, etc) since we only use the AXI-Stream ports
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#pragma HLS INTERFACE ap_ctrl_none port=return
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// Set ports as AXI-Stream
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#pragma HLS INTERFACE axis port=sub
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#pragma HLS INTERFACE axis port=add
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#pragma HLS INTERFACE axis port=a
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#pragma HLS INTERFACE axis port=b
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// Need to pack our complex<short int> into a 32-bit word
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// Otherwise, compiler complains that our AXI-Stream interfaces have two data fields (i.e. data.real, data.imag)
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#pragma HLS DATA_PACK variable=sub.data
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#pragma HLS DATA_PACK variable=add.data
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#pragma HLS DATA_PACK variable=a.data
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#pragma HLS DATA_PACK variable=b.data
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// Set ports as AXI-Stream
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#pragma HLS INTERFACE axis port = sub
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#pragma HLS INTERFACE axis port = add
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#pragma HLS INTERFACE axis port = a
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#pragma HLS INTERFACE axis port = b
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// Complex add / subtract
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add.data.real() = a.data.real() + b.data.real();
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add.data.imag() = a.data.imag() + b.data.imag();
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sub.data.real() = a.data.real() - b.data.real();
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sub.data.imag() = a.data.imag() - b.data.imag();
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// Pass through tlast
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add.last = a.last;
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sub.last = a.last;
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trans_pkt a_pkt;
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a.read(a_pkt);
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trans_pkt b_pkt;
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b.read(b_pkt);
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trans_pkt add_pkt;
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add_pkt.data = {
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a_pkt.data.real() + b_pkt.data.real(),
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a_pkt.data.imag() + b_pkt.data.imag()};
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add_pkt.last = a_pkt.last;
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add.write(add_pkt);
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trans_pkt sub_pkt;
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sub_pkt.data = {
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a_pkt.data.real() - b_pkt.data.real(),
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a_pkt.data.imag() - b_pkt.data.imag()};
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sub_pkt.last = a_pkt.last;
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sub.write(sub_pkt);
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}
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