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fpga: lib: Upgrade to Vivado 2021.1

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Original-commit: b0dc0faed1eceef3ba28ce03555658fca2423c46
This commit is contained in:
Sam O'Brien authored and skooNI committed 2022-08-25 13:55:30 -05:00
1 parent f53e3f27fc
commit a63c80bd23
24 files changed
+543 -177
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lib/axi4s_sv/axi4s_add_bytes.sv
+5 -5
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@@ -83,11 +83,11 @@ module axi4s_add_bytes #(
logic reached_start;
logic reached_end;
logic byte_overflow;
logic [s0.DATA_WIDTH-1:0] zero_data;
logic [s0.DATA_WIDTH-1:0] last_tdata;
logic [s0.DATA_WIDTH-1:0] remaining_shift_data;
logic [s0.DATA_WIDTH-1:0] last_shift_data;
logic [s0.DATA_WIDTH-1:0] first_shifted_data;
logic [i.DATA_WIDTH-1:0] zero_data;
logic [i.DATA_WIDTH-1:0] last_tdata;
logic [i.DATA_WIDTH-1:0] remaining_shift_data;
logic [i.DATA_WIDTH-1:0] last_shift_data;
logic [i.DATA_WIDTH-1:0] first_shifted_data;
logic error_bit, error_bit_old;