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fpga: rfnoc: Add RFNoC Add/Sub block

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Original-commit: 5134b6caea58da825c4da1888a4d26888acc126a
This commit is contained in:
Wade Fife
2020-05-28 15:04:05 -05:00
committed by Aaron Rossetto
parent 859accafb3
commit a46e351a65
7 changed files with 1190 additions and 10 deletions
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lib/hls/addsub_hls/Makefile.inc
+7 -10
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@@ -1,22 +1,19 @@
#
# Copyright 2015-2017 Ettus Research
# Copyright 2016 Ettus Research, a National Instruments Company
# Copyright 2020 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Add C/C++/tcl files relative to usrp3/lib/hls/<ip> directory
HLS_IP_ADDSUB_HLS_SRCS = \
HLS_IP_ADDSUB_HLS_LIB_SRCS = $(addprefix $(HLS_IP_DIR)/addsub_hls/, \
addsub_hls.cpp \
addsub_hls.tcl
HLS_IP_ADDSUB_HLS_OUTS = $(addprefix $(IP_BUILD_DIR)/addsub_hls/, \
solution/impl/verilog/addsub_hls.v \
addsub_hls.tcl \
)
# Sources in lib directory
HLS_IP_ADDSUB_HLS_LIB_SRCS = $(addprefix $(HLS_IP_DIR)/addsub_hls/, $(HLS_IP_ADDSUB_HLS_SRCS))
# HLS output artifact points to the ip/hdl/verilog folder. The build process
# will glob all the files in this directory, including *.dat files.
HLS_IP_ADDSUB_HLS_OUTS = $(IP_BUILD_DIR)/addsub_hls/solution/impl/ip/hdl/verilog
# Build with HLS
$(HLS_IP_ADDSUB_HLS_OUTS) : $(HLS_IP_ADDSUB_HLS_LIB_SRCS)
$(call BUILD_VIVADO_HLS_IP,addsub_hls,$(PART_ID),$(HLS_IP_ADDSUB_HLS_LIB_SRCS),$(HLS_IP_DIR),$(IP_BUILD_DIR),)
$(call BUILD_VIVADO_HLS_IP,addsub_hls,$(PART_ID),$(HLS_IP_ADDSUB_HLS_LIB_SRCS),$(HLS_IP_DIR),$(IP_BUILD_DIR),)