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fpga: n3xx: Support advanced transport adapter

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- Fix NODE_INST
- Fix RFNOC_PROTOVER
- Add option to use SystemVerilog transport adapter for raw UDP


Original-commit: 693ec2c896306bcba3686385e5861593040d4cbd
This commit is contained in:
Wade Fife
2022-08-29 17:01:45 -05:00
committed by skooNI
parent 6981891978
commit a270cb29d6
5 changed files with 426 additions and 305 deletions
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top/n3xx/Makefile.n3xx.inc
+5 -1
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@@ -37,6 +37,9 @@ include $(LIB_DIR)/rfnoc/Makefile.srcs
include $(BASE_DIR)/n3xx/dboards/rh/Makefile.srcs include $(BASE_DIR)/n3xx/dboards/rh/Makefile.srcs
include $(BASE_DIR)/n3xx/dboards/mg/Makefile.srcs include $(BASE_DIR)/n3xx/dboards/mg/Makefile.srcs
include $(BASE_DIR)/n3xx/dboards/common/Makefile.srcs include $(BASE_DIR)/n3xx/dboards/common/Makefile.srcs
include $(LIB_DIR)/axi4s_sv/Makefile.srcs
include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and # For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
# DUC, Replay, and of course the radio. Any other block needs to use the # DUC, Replay, and of course the radio. Any other block needs to use the
# RFNOC_OOT_MAKEFILE_SRCS variable (see below). # RFNOC_OOT_MAKEFILE_SRCS variable (see below).
@@ -139,7 +142,8 @@ $(RFNOC_FRAMEWORK_SRCS) \
$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \ $(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \ $(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \
$(RFNOC_BLOCK_RADIO_SRCS) \ $(RFNOC_BLOCK_RADIO_SRCS) \
$(RFNOC_BLOCK_REPLAY_SRCS) $(RFNOC_BLOCK_REPLAY_SRCS) \
$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))" EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))" IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
top/n3xx/dboards/mg/n3xx.v
+12 -4
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@@ -1178,7 +1178,9 @@ module n3xx (
.LANES (NUM_QSFP_LANES), .LANES (NUM_QSFP_LANES),
.PORTNUM_BASE (4), .PORTNUM_BASE (4),
.REG_DWIDTH (REG_DWIDTH), .REG_DWIDTH (REG_DWIDTH),
.REG_AWIDTH (QSFP_REG_AWIDTH) .REG_AWIDTH (QSFP_REG_AWIDTH),
.RFNOC_PROTOVER (RFNOC_PROTOVER),
.NODE_INST_BASE (0)
) qsfp_wrapper_i ( ) qsfp_wrapper_i (
.areset (global_rst), .areset (global_rst),
.gt_refclk (qsfp_gt_refclk), .gt_refclk (qsfp_gt_refclk),
@@ -1694,7 +1696,9 @@ module n3xx (
`endif `endif
.REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
.REG_AWIDTH(REG_AWIDTH), // Width of the address bus .REG_AWIDTH(REG_AWIDTH), // Width of the address bus
.PORTNUM_BASE(8'd0) .PORTNUM_BASE(8'd0),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST_BASE(0)
) sfp_wrapper_0 ( ) sfp_wrapper_0 (
.areset(global_rst), .areset(global_rst),
.gt_refclk(sfp0_gt_refclk), .gt_refclk(sfp0_gt_refclk),
@@ -1865,7 +1869,9 @@ module n3xx (
`endif `endif
.REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
.REG_AWIDTH(REG_AWIDTH), // Width of the address bus .REG_AWIDTH(REG_AWIDTH), // Width of the address bus
.PORTNUM_BASE(8'd1) .PORTNUM_BASE(8'd1),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST_BASE(1)
) sfp_wrapper_1 ( ) sfp_wrapper_1 (
.areset(global_rst), .areset(global_rst),
@@ -2576,7 +2582,9 @@ module n3xx (
eth_internal #( eth_internal #(
.DWIDTH(REG_DWIDTH), .DWIDTH(REG_DWIDTH),
.AWIDTH(REG_AWIDTH), .AWIDTH(REG_AWIDTH),
.PORTNUM(8'd1) .PORTNUM(8'd1),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST(2)
) eth_internal_i ( ) eth_internal_i (
// Resets // Resets
.bus_rst (bus_rst), .bus_rst (bus_rst),
top/n3xx/dboards/rh/n3xx.v
+12 -4
View File
@@ -1168,7 +1168,9 @@ module n3xx (
.GT_COMMON (1), .GT_COMMON (1),
.PORTNUM_BASE (4), .PORTNUM_BASE (4),
.REG_DWIDTH (REG_DWIDTH), .REG_DWIDTH (REG_DWIDTH),
.REG_AWIDTH (QSFP_REG_AWIDTH) .REG_AWIDTH (QSFP_REG_AWIDTH),
.RFNOC_PROTOVER (RFNOC_PROTOVER),
.NODE_INST_BASE (0)
) qsfp_wrapper_i ( ) qsfp_wrapper_i (
.areset (global_rst), .areset (global_rst),
.gt_refclk (qsfp_gt_refclk), .gt_refclk (qsfp_gt_refclk),
@@ -1685,7 +1687,9 @@ module n3xx (
.REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
.REG_AWIDTH(REG_AWIDTH), // Width of the address bus .REG_AWIDTH(REG_AWIDTH), // Width of the address bus
.GT_COMMON(1), .GT_COMMON(1),
.PORTNUM_BASE(8'd0) .PORTNUM_BASE(8'd0),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST_BASE(0)
) sfp_wrapper_0 ( ) sfp_wrapper_0 (
.areset(global_rst), .areset(global_rst),
.gt_refclk(sfp0_gt_refclk), .gt_refclk(sfp0_gt_refclk),
@@ -1856,7 +1860,9 @@ module n3xx (
.REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
.REG_AWIDTH(REG_AWIDTH), // Width of the address bus .REG_AWIDTH(REG_AWIDTH), // Width of the address bus
.GT_COMMON(1), .GT_COMMON(1),
.PORTNUM_BASE(8'd1) .PORTNUM_BASE(8'd1),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST_BASE(1)
) sfp_wrapper_1 ( ) sfp_wrapper_1 (
.areset(global_rst), .areset(global_rst),
@@ -2567,7 +2573,9 @@ module n3xx (
eth_internal #( eth_internal #(
.DWIDTH(REG_DWIDTH), .DWIDTH(REG_DWIDTH),
.AWIDTH(REG_AWIDTH), .AWIDTH(REG_AWIDTH),
.PORTNUM(8'd1) .PORTNUM(8'd1),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST(2)
) eth_internal_i ( ) eth_internal_i (
// Resets // Resets
.bus_rst (bus_rst), .bus_rst (bus_rst),
top/n3xx/n3xx_mgt_channel_wrapper.v
+31 -13
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@@ -1,27 +1,44 @@
///////////////////////////////////////////////////////////////////
// //
// Copyright 2018 Ettus Research, A National Instruments Company // Copyright 2018 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
// Module: n3xx_mgt_channel_wrapper // Module: n3xx_mgt_channel_wrapper
//
// Description: // Description:
//
// Aurora/10 GbE wrapper for up to 4 QSFP lanes -or- // Aurora/10 GbE wrapper for up to 4 QSFP lanes -or-
// Aurora/1 GbE/10 GbE/White Rabbit wrapper for 1 SFP+ lane // Aurora/1 GbE/10 GbE/White Rabbit wrapper for 1 SFP+ lane
// //
////////////////////////////////////////////////////////////////////// // Parameters:
//
// PROTOCOL : Must be {10GbE, Aurora, Disabled}
// LANES : Number of lanes of to instantiate (1, 2, 3, or 4)
// REG_BASE : Base register address
// PORTNUM_BASE : Base port number for discovery
// MDIO_EN : Enable MDIO port
// MDIO_PHYADDR : MDIO address to use
// REG_DWIDTH : Width of regport address bus
// REG_AWIDTH : Width of regport data bus
// GT_COMMON : Use GT Common ports on MGT
// RFNOC_PROTOVER : RFNoC protocol version to be reported by transport
// adapters.
// NODE_INST : RFNoC transport adapter node instance for this port
//
`default_nettype none `default_nettype none
module n3xx_mgt_channel_wrapper #( module n3xx_mgt_channel_wrapper #(
parameter PROTOCOL = "10GbE",// Must be {10GbE, Aurora, Disabled} parameter PROTOCOL = "10GbE",
parameter LANES = 2, // Number of lanes of to instantiate (Supported = {1,2,3,4}) parameter LANES = 2,
parameter REG_BASE = 32'h0, // Base register address parameter REG_BASE = 32'h0,
parameter PORTNUM_BASE = 4, // Base port number for discovery parameter PORTNUM_BASE = 4,
parameter MDIO_EN = 1, // Enable MDIO port parameter MDIO_EN = 1,
parameter [4:0] MDIO_PHYADDR = 5'd0, // Enable MDIO port parameter [ 4:0] MDIO_PHYADDR = 5'd0,
parameter REG_DWIDTH = 32, // Width of regport address bus parameter REG_DWIDTH = 32,
parameter REG_AWIDTH = 14, // Width of regport data bus parameter REG_AWIDTH = 14,
parameter GT_COMMON = 1 parameter GT_COMMON = 1,
parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0},
parameter NODE_INST_BASE = 0
)( )(
// Resets // Resets
input wire areset, input wire areset,
@@ -275,7 +292,8 @@ module n3xx_mgt_channel_wrapper #(
.GT_COMMON (GT_COMMON), .GT_COMMON (GT_COMMON),
.MDIO_EN (MDIO_EN), .MDIO_EN (MDIO_EN),
.MDIO_PHYADDR (MDIO_PHYADDR), .MDIO_PHYADDR (MDIO_PHYADDR),
.PORTNUM (PORTNUM_BASE + l) .PORTNUM (PORTNUM_BASE + l),
.NODE_INST (NODE_INST_BASE + l)
) lane_i ( ) lane_i (
//must reset all channels on quad when sfp1 gtx core is reset //must reset all channels on quad when sfp1 gtx core is reset
.areset (areset), .areset (areset),
top/n3xx/n3xx_mgt_wrapper.v
+104 -21
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@@ -1,27 +1,48 @@
///////////////////////////////////////////////////////////////////
// //
// Copyright 2018 Ettus Research, A National Instruments Company // Copyright 2018 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
// Module: n3xx_mgt_wrapper // Module: n3xx_mgt_wrapper
// Description:
// Provides wrapper for just the pieces specific to an MGT lane
// (for easy use with generate)
// //
////////////////////////////////////////////////////////////////////// // Description:
//
// Wrapper for single MGT, including support for Aurora, WhiteRabbit, 10 GbE,
// and 1 GbE.
//
// Parameters:
//
// PROTOCOL : Must be "10GbE", "1GbE", "Aurora", or "Disabled".
// REG_DWIDTH : Data width of the AXI-Lite interface and RegPort
// REG_AWIDTH : Address width of the AXI-Lite interface and RegPort\
// GT_COMMON : Use GT Common ports on MGT
// PORTNUM : Port number
// MDIO_EN : Enables internal MDIO master
// MDIO_PHYADDR : Address to use for the MDIO
// RFNOC_PROTOVER : RFNoC protocol version to be reported by transport
// adapters.
// NODE_INST : RFNoC transport adapter node instance for this port
// EN_RX_KV_MAP_CFG : Enable KV-map configuration port on transport adapter
// EN_RX_RAW_PYLD : Enable raw UDP support on transport adapter
//
`default_nettype none `default_nettype none
module n3xx_mgt_wrapper #( module n3xx_mgt_wrapper #(
parameter PROTOCOL = "10GbE", // Must be {10GbE, Aurora, Disabled} parameter PROTOCOL = "10GbE",
parameter REG_DWIDTH = 32, parameter REG_DWIDTH = 32,
parameter REG_AWIDTH = 14, parameter REG_AWIDTH = 14,
parameter REG_BASE = 16'h0000,
parameter GT_COMMON = 1, parameter GT_COMMON = 1,
parameter [7:0] PORTNUM = 8'd0, parameter [ 7:0] PORTNUM = 8'd0,
parameter MDIO_EN = 0, parameter MDIO_EN = 0,
parameter [4:0] MDIO_PHYADDR = 5'd0, parameter [ 4:0] MDIO_PHYADDR = 5'd0,
parameter REG_BASE = 16'h0000 parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0},
)( parameter NODE_INST = 0,
parameter EN_RX_KV_MAP_CFG = 1,
parameter EN_RX_RAW_PYLD = 1
) (
// Resets // Resets
input wire areset, input wire areset,
input wire bus_rst, input wire bus_rst,
@@ -378,13 +399,13 @@ module n3xx_mgt_wrapper #(
// Converting tuser to tkeep for ingress packets // Converting tuser to tkeep for ingress packets
assign e2c_tkeep = ~e2c_tlast ? 8'b1111_1111 assign e2c_tkeep = ~e2c_tlast ? 8'b1111_1111
: (e2c_tuser == 4'd0) ? 8'b1111_1111 : (e2c_tuser[2:0] == 3'd0) ? 8'b1111_1111
: (e2c_tuser == 4'd1) ? 8'b0000_0001 : (e2c_tuser[2:0] == 3'd1) ? 8'b0000_0001
: (e2c_tuser == 4'd2) ? 8'b0000_0011 : (e2c_tuser[2:0] == 3'd2) ? 8'b0000_0011
: (e2c_tuser == 4'd3) ? 8'b0000_0111 : (e2c_tuser[2:0] == 3'd3) ? 8'b0000_0111
: (e2c_tuser == 4'd4) ? 8'b0000_1111 : (e2c_tuser[2:0] == 3'd4) ? 8'b0000_1111
: (e2c_tuser == 4'd5) ? 8'b0001_1111 : (e2c_tuser[2:0] == 3'd5) ? 8'b0001_1111
: (e2c_tuser == 4'd6) ? 8'b0011_1111 : (e2c_tuser[2:0] == 3'd6) ? 8'b0011_1111
: 8'b0111_1111; : 8'b0111_1111;
// Converting tkeep to tuser for egress packets // Converting tkeep to tuser for egress packets
@@ -399,10 +420,70 @@ module n3xx_mgt_wrapper #(
: (c2e_tkeep == 8'b0000_0001) ? 4'd1 : (c2e_tkeep == 8'b0000_0001) ? 4'd1
: 4'd0; : 4'd0;
if (EN_RX_KV_MAP_CFG || EN_RX_RAW_PYLD) begin : gen_eth_ipv4_interface_wrapper
eth_ipv4_interface_wrapper #(
.PROTOVER (RFNOC_PROTOVER),
.NODE_INST (NODE_INST),
.REG_AWIDTH (REG_AWIDTH),
.BASE (REG_BASE_ETH_SWITCH),
.SYNC (1),
.EN_RX_KV_MAP_CFG (EN_RX_KV_MAP_CFG),
.EN_RX_RAW_PYLD (EN_RX_RAW_PYLD)
) eth_ipv4_interface_wrapper_i (
.bus_clk (bus_clk),
.bus_rst (bus_rst),
.device_id (device_id),
.reg_wr_req (reg_wr_req),
.reg_wr_addr (reg_wr_addr),
.reg_wr_data (reg_wr_data),
.reg_rd_req (reg_rd_req),
.reg_rd_addr (reg_rd_addr),
.reg_rd_resp (reg_rd_resp_eth_if),
.reg_rd_data (reg_rd_data_eth_if),
.my_mac (),
.my_ip (),
.my_udp_chdr_port (),
.eth_clk (bus_clk),
.eth_rst (bus_rst),
.eth_pause_req (),
.eth_tx_tdata (mgti_tdata),
.eth_tx_tuser (mgti_tuser),
.eth_tx_tkeep (),
.eth_tx_tlast (mgti_tlast),
.eth_tx_tvalid (mgti_tvalid),
.eth_tx_tready (mgti_tready),
.eth_rx_tdata (mgto_tdata),
.eth_rx_tuser (mgto_tuser),
.eth_rx_tlast (mgto_tlast),
.eth_rx_tvalid (mgto_tvalid),
.eth_rx_tready (mgto_tready),
.e2v_tdata (e2v_tdata),
.e2v_tlast (e2v_tlast),
.e2v_tvalid (e2v_tvalid),
.e2v_tready (e2v_tready),
.v2e_tdata (v2e_tdata),
.v2e_tlast (v2e_tlast),
.v2e_tvalid (v2e_tvalid),
.v2e_tready (v2e_tready),
.cpu_clk (bus_clk),
.cpu_rst (bus_rst),
.e2c_tdata (e2c_tdata),
.e2c_tuser (e2c_tuser),
.e2c_tlast (e2c_tlast),
.e2c_tvalid (e2c_tvalid),
.e2c_tready (e2c_tready),
.c2e_tdata (c2e_tdata),
.c2e_tuser (c2e_tuser),
.c2e_tlast (c2e_tlast),
.c2e_tvalid (c2e_tvalid),
.c2e_tready (c2e_tready)
);
end // gen_eth_ipv4_interface_wrapper
else begin : gen_eth_interface
eth_interface #( eth_interface #(
.PROTOVER ({8'd1,8'd0}), //FIXME. This should come from outside .PROTOVER (RFNOC_PROTOVER),
.MTU (10), .MTU (10),
.NODE_INST (0), .NODE_INST (NODE_INST),
.REG_AWIDTH (REG_AWIDTH), .REG_AWIDTH (REG_AWIDTH),
.BASE (REG_BASE_ETH_SWITCH) .BASE (REG_BASE_ETH_SWITCH)
) eth_interface ( ) eth_interface (
@@ -448,9 +529,11 @@ module n3xx_mgt_wrapper #(
.c2e_tvalid (c2e_tvalid), .c2e_tvalid (c2e_tvalid),
.c2e_tready (c2e_tready) .c2e_tready (c2e_tready)
); );
end // gen_eth_interface
end end
endgenerate endgenerate
endmodule // n3xx_mgt_wrapper endmodule // n3xx_mgt_wrapper
`default_nettype wire `default_nettype wire