From a270cb29d6e73245add5892ad58db1fd2b6e724f Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Tue, 31 May 2022 16:44:35 -0500 Subject: [PATCH] fpga: n3xx: Support advanced transport adapter - Fix NODE_INST - Fix RFNOC_PROTOVER - Add option to use SystemVerilog transport adapter for raw UDP Original-commit: 693ec2c896306bcba3686385e5861593040d4cbd --- top/n3xx/Makefile.n3xx.inc | 6 +- top/n3xx/dboards/mg/n3xx.v | 262 ++++++++++++++-------------- top/n3xx/dboards/rh/n3xx.v | 178 ++++++++++--------- top/n3xx/n3xx_mgt_channel_wrapper.v | 58 +++--- top/n3xx/n3xx_mgt_wrapper.v | 227 ++++++++++++++++-------- 5 files changed, 426 insertions(+), 305 deletions(-) diff --git a/top/n3xx/Makefile.n3xx.inc b/top/n3xx/Makefile.n3xx.inc index 34b31aa..45b7234 100644 --- a/top/n3xx/Makefile.n3xx.inc +++ b/top/n3xx/Makefile.n3xx.inc @@ -37,6 +37,9 @@ include $(LIB_DIR)/rfnoc/Makefile.srcs include $(BASE_DIR)/n3xx/dboards/rh/Makefile.srcs include $(BASE_DIR)/n3xx/dboards/mg/Makefile.srcs include $(BASE_DIR)/n3xx/dboards/common/Makefile.srcs +include $(LIB_DIR)/axi4s_sv/Makefile.srcs +include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs + # For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and # DUC, Replay, and of course the radio. Any other block needs to use the # RFNOC_OOT_MAKEFILE_SRCS variable (see below). @@ -139,7 +142,8 @@ $(RFNOC_FRAMEWORK_SRCS) \ $(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \ $(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \ $(RFNOC_BLOCK_RADIO_SRCS) \ -$(RFNOC_BLOCK_REPLAY_SRCS) +$(RFNOC_BLOCK_REPLAY_SRCS) \ +$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \ EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))" IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))" diff --git a/top/n3xx/dboards/mg/n3xx.v b/top/n3xx/dboards/mg/n3xx.v index c42de40..59ddff5 100644 --- a/top/n3xx/dboards/mg/n3xx.v +++ b/top/n3xx/dboards/mg/n3xx.v @@ -1178,7 +1178,9 @@ module n3xx ( .LANES (NUM_QSFP_LANES), .PORTNUM_BASE (4), .REG_DWIDTH (REG_DWIDTH), - .REG_AWIDTH (QSFP_REG_AWIDTH) + .REG_AWIDTH (QSFP_REG_AWIDTH), + .RFNOC_PROTOVER (RFNOC_PROTOVER), + .NODE_INST_BASE (0) ) qsfp_wrapper_i ( .areset (global_rst), .gt_refclk (qsfp_gt_refclk), @@ -1694,147 +1696,149 @@ module n3xx ( `endif .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) .REG_AWIDTH(REG_AWIDTH), // Width of the address bus - .PORTNUM_BASE(8'd0) - ) sfp_wrapper_0 ( - .areset(global_rst), - .gt_refclk(sfp0_gt_refclk), - .gb_refclk(sfp0_gb_refclk), - .misc_clk(sfp0_misc_clk), - .user_clk(au_user_clk), - .sync_clk(au_sync_clk), - .gt_tx_out_clk_unbuf(sfp0_tx_out_clk), + .PORTNUM_BASE(8'd0), + .RFNOC_PROTOVER(RFNOC_PROTOVER), + .NODE_INST_BASE(0) + ) sfp_wrapper_0 ( + .areset(global_rst), + .gt_refclk(sfp0_gt_refclk), + .gb_refclk(sfp0_gb_refclk), + .misc_clk(sfp0_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp0_tx_out_clk), - .bus_rst(bus_rst), - .bus_clk(bus_clk), + .bus_rst(bus_rst), + .bus_clk(bus_clk), - .qpllreset(qpllreset_sfp0), - .qplllock(qplllock), - .qplloutclk(qplloutclk), - .qplloutrefclk(qplloutrefclk), - .qpllrefclklost(), + .qpllreset(qpllreset_sfp0), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), - .mmcm_locked(au_mmcm_locked), - .gt_pll_lock(sfp0_gt_pll_lock), + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp0_gt_pll_lock), - .txp(SFP_0_TX_P), - .txn(SFP_0_TX_N), - .rxp(SFP_0_RX_P), - .rxn(SFP_0_RX_N), + .txp(SFP_0_TX_P), + .txn(SFP_0_TX_N), + .rxp(SFP_0_RX_P), + .rxn(SFP_0_RX_N), - .mod_present_n(SFP_0_I2C_NPRESENT), - .mod_rxlos(SFP_0_LOS), - .mod_tx_fault(SFP_0_TXFAULT), - .mod_tx_disable(SFP_0_TXDISABLE), + .mod_present_n(SFP_0_I2C_NPRESENT), + .mod_rxlos(SFP_0_LOS), + .mod_tx_fault(SFP_0_TXFAULT), + .mod_tx_disable(SFP_0_TXDISABLE), - // Clock and reset - .s_axi_aclk(clk40), - .s_axi_aresetn(clk40_rstn), - // AXI4-Lite: Write address port (domain: s_axi_aclk) - .s_axi_awaddr(M_AXI_NET0_AWADDR[REG_AWIDTH-1:0]), - .s_axi_awvalid(M_AXI_NET0_AWVALID), - .s_axi_awready(M_AXI_NET0_AWREADY), - // AXI4-Lite: Write data port (domain: s_axi_aclk) - .s_axi_wdata(M_AXI_NET0_WDATA), - .s_axi_wstrb(M_AXI_NET0_WSTRB), - .s_axi_wvalid(M_AXI_NET0_WVALID), - .s_axi_wready(M_AXI_NET0_WREADY), - // AXI4-Lite: Write response port (domain: s_axi_aclk) - .s_axi_bresp(M_AXI_NET0_BRESP), - .s_axi_bvalid(M_AXI_NET0_BVALID), - .s_axi_bready(M_AXI_NET0_BREADY), - // AXI4-Lite: Read address port (domain: s_axi_aclk) - .s_axi_araddr(M_AXI_NET0_ARADDR[REG_AWIDTH-1:0]), - .s_axi_arvalid(M_AXI_NET0_ARVALID), - .s_axi_arready(M_AXI_NET0_ARREADY), - // AXI4-Lite: Read data port (domain: s_axi_aclk) - .s_axi_rdata(M_AXI_NET0_RDATA), - .s_axi_rresp(M_AXI_NET0_RRESP), - .s_axi_rvalid(M_AXI_NET0_RVALID), - .s_axi_rready(M_AXI_NET0_RREADY), + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET0_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET0_AWVALID), + .s_axi_awready(M_AXI_NET0_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET0_WDATA), + .s_axi_wstrb(M_AXI_NET0_WSTRB), + .s_axi_wvalid(M_AXI_NET0_WVALID), + .s_axi_wready(M_AXI_NET0_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET0_BRESP), + .s_axi_bvalid(M_AXI_NET0_BVALID), + .s_axi_bready(M_AXI_NET0_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET0_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET0_ARVALID), + .s_axi_arready(M_AXI_NET0_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET0_RDATA), + .s_axi_rresp(M_AXI_NET0_RRESP), + .s_axi_rvalid(M_AXI_NET0_RVALID), + .s_axi_rready(M_AXI_NET0_RREADY), - // Ethernet to Vita - .e2v_tdata(e2v_sfp0_tdata), - .e2v_tlast(e2v_sfp0_tlast), - .e2v_tvalid(e2v_sfp0_tvalid), - .e2v_tready(e2v_sfp0_tready), + // Ethernet to Vita + .e2v_tdata(e2v_sfp0_tdata), + .e2v_tlast(e2v_sfp0_tlast), + .e2v_tvalid(e2v_sfp0_tvalid), + .e2v_tready(e2v_sfp0_tready), - // Vita to Ethernet - .v2e_tdata(v2e_sfp0_tdata), - .v2e_tlast(v2e_sfp0_tlast), - .v2e_tvalid(v2e_sfp0_tvalid), - .v2e_tready(v2e_sfp0_tready), + // Vita to Ethernet + .v2e_tdata(v2e_sfp0_tdata), + .v2e_tlast(v2e_sfp0_tlast), + .v2e_tvalid(v2e_sfp0_tvalid), + .v2e_tready(v2e_sfp0_tready), - // Ethernet to CPU - .e2c_tdata(arm_eth_sfp0_rx_tdata_b), - .e2c_tkeep(arm_eth_sfp0_rx_tkeep_b), - .e2c_tlast(arm_eth_sfp0_rx_tlast_b), - .e2c_tvalid(arm_eth_sfp0_rx_tvalid_b), - .e2c_tready(arm_eth_sfp0_rx_tready_b), + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp0_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp0_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp0_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp0_rx_tvalid_b), + .e2c_tready(arm_eth_sfp0_rx_tready_b), - // CPU to Ethernet - .c2e_tdata(arm_eth_sfp0_tx_tdata_b), - .c2e_tkeep(arm_eth_sfp0_tx_tkeep_b), - .c2e_tlast(arm_eth_sfp0_tx_tlast_b), - .c2e_tvalid(arm_eth_sfp0_tx_tvalid_b), - .c2e_tready(arm_eth_sfp0_tx_tready_b), + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp0_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp0_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp0_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp0_tx_tvalid_b), + .c2e_tready(arm_eth_sfp0_tx_tready_b), - // White Rabbit Specific + // White Rabbit Specific `ifdef SFP0_WR - .wr_reset_n (~ps_gpio_out[48]), // reset for WR only - .wr_refclk (wr_refclk_buf), - .wr_dac_sclk (WB_DAC_SCLK), - .wr_dac_din (WB_DAC_DIN), - .wr_dac_clr_n (WB_DAC_NCLR), - .wr_dac_cs_n (WB_DAC_NSYNC), - .wr_dac_ldac_n(WB_DAC_NLDAC), - .wr_eeprom_scl_o(), // storage for delay characterization - .wr_eeprom_scl_i(1'b0), // temp - .wr_eeprom_sda_o(), - .wr_eeprom_sda_i(1'b0), // temp - .wr_uart_rx(wr_uart_rxd), // to/from PS - .wr_uart_tx(wr_uart_txd), - .mod_pps(pps_wr_refclk), // out, reference clock and pps - .mod_refclk(wr_ref_clk), - // WR Slave Port to PS - .wr_axi_aclk(m_axi_wr_clk), // out to PS - .wr_axi_aresetn(1'b1), // in - .wr_axi_awaddr(m_axi_wr_awaddr), - .wr_axi_awvalid(m_axi_wr_awvalid), - .wr_axi_awready(m_axi_wr_awready), - .wr_axi_wdata(m_axi_wr_wdata), - .wr_axi_wstrb(m_axi_wr_wstrb), - .wr_axi_wvalid(m_axi_wr_wvalid), - .wr_axi_wready(m_axi_wr_wready), - .wr_axi_bresp(m_axi_wr_bresp), - .wr_axi_bvalid(m_axi_wr_bvalid), - .wr_axi_bready(m_axi_wr_bready), - .wr_axi_araddr(m_axi_wr_araddr), - .wr_axi_arvalid(m_axi_wr_arvalid), - .wr_axi_arready(m_axi_wr_arready), - .wr_axi_rdata(m_axi_wr_rdata), - .wr_axi_rresp(m_axi_wr_rresp), - .wr_axi_rvalid(m_axi_wr_rvalid), - .wr_axi_rready(m_axi_wr_rready), - .wr_axi_rlast(), + .wr_reset_n (~ps_gpio_out[48]), // reset for WR only + .wr_refclk (wr_refclk_buf), + .wr_dac_sclk (WB_DAC_SCLK), + .wr_dac_din (WB_DAC_DIN), + .wr_dac_clr_n (WB_DAC_NCLR), + .wr_dac_cs_n (WB_DAC_NSYNC), + .wr_dac_ldac_n(WB_DAC_NLDAC), + .wr_eeprom_scl_o(), // storage for delay characterization + .wr_eeprom_scl_i(1'b0), // temp + .wr_eeprom_sda_o(), + .wr_eeprom_sda_i(1'b0), // temp + .wr_uart_rx(wr_uart_rxd), // to/from PS + .wr_uart_tx(wr_uart_txd), + .mod_pps(pps_wr_refclk), // out, reference clock and pps + .mod_refclk(wr_ref_clk), + // WR Slave Port to PS + .wr_axi_aclk(m_axi_wr_clk), // out to PS + .wr_axi_aresetn(1'b1), // in + .wr_axi_awaddr(m_axi_wr_awaddr), + .wr_axi_awvalid(m_axi_wr_awvalid), + .wr_axi_awready(m_axi_wr_awready), + .wr_axi_wdata(m_axi_wr_wdata), + .wr_axi_wstrb(m_axi_wr_wstrb), + .wr_axi_wvalid(m_axi_wr_wvalid), + .wr_axi_wready(m_axi_wr_wready), + .wr_axi_bresp(m_axi_wr_bresp), + .wr_axi_bvalid(m_axi_wr_bvalid), + .wr_axi_bready(m_axi_wr_bready), + .wr_axi_araddr(m_axi_wr_araddr), + .wr_axi_arvalid(m_axi_wr_arvalid), + .wr_axi_arready(m_axi_wr_arready), + .wr_axi_rdata(m_axi_wr_rdata), + .wr_axi_rresp(m_axi_wr_rresp), + .wr_axi_rvalid(m_axi_wr_rvalid), + .wr_axi_rready(m_axi_wr_rready), + .wr_axi_rlast(), `else - .wr_reset_n(1'b1), - .wr_refclk(1'b0), - .wr_eeprom_scl_i(1'b0), - .wr_eeprom_sda_i(1'b0), - .wr_uart_rx(1'b0), + .wr_reset_n(1'b1), + .wr_refclk(1'b0), + .wr_eeprom_scl_i(1'b0), + .wr_eeprom_sda_i(1'b0), + .wr_uart_rx(1'b0), `endif - // Misc - .port_info(sfp_port0_info), - .device_id(device_id), + // Misc + .port_info(sfp_port0_info), + .device_id(device_id), - // LED - .link_up(sfp0_link_up), - .activity(SFP_0_LED_A) - ); + // LED + .link_up(sfp0_link_up), + .activity(SFP_0_LED_A) + ); - assign ps_gpio_in[60] = ps_gpio_tri[60] ? sfp0_link_up : ps_gpio_out[60]; - assign SFP_0_LED_B = sfp0_link_up; + assign ps_gpio_in[60] = ps_gpio_tri[60] ? sfp0_link_up : ps_gpio_out[60]; + assign SFP_0_LED_B = sfp0_link_up; `ifndef SFP0_WR assign WB_DAC_SCLK = 1'b0; @@ -1865,7 +1869,9 @@ module n3xx ( `endif .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) .REG_AWIDTH(REG_AWIDTH), // Width of the address bus - .PORTNUM_BASE(8'd1) + .PORTNUM_BASE(8'd1), + .RFNOC_PROTOVER(RFNOC_PROTOVER), + .NODE_INST_BASE(1) ) sfp_wrapper_1 ( .areset(global_rst), @@ -2576,7 +2582,9 @@ module n3xx ( eth_internal #( .DWIDTH(REG_DWIDTH), .AWIDTH(REG_AWIDTH), - .PORTNUM(8'd1) + .PORTNUM(8'd1), + .RFNOC_PROTOVER(RFNOC_PROTOVER), + .NODE_INST(2) ) eth_internal_i ( // Resets .bus_rst (bus_rst), diff --git a/top/n3xx/dboards/rh/n3xx.v b/top/n3xx/dboards/rh/n3xx.v index e5238f1..7aa5ff0 100644 --- a/top/n3xx/dboards/rh/n3xx.v +++ b/top/n3xx/dboards/rh/n3xx.v @@ -1168,7 +1168,9 @@ module n3xx ( .GT_COMMON (1), .PORTNUM_BASE (4), .REG_DWIDTH (REG_DWIDTH), - .REG_AWIDTH (QSFP_REG_AWIDTH) + .REG_AWIDTH (QSFP_REG_AWIDTH), + .RFNOC_PROTOVER (RFNOC_PROTOVER), + .NODE_INST_BASE (0) ) qsfp_wrapper_i ( .areset (global_rst), .gt_refclk (qsfp_gt_refclk), @@ -1685,7 +1687,9 @@ module n3xx ( .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) .REG_AWIDTH(REG_AWIDTH), // Width of the address bus .GT_COMMON(1), - .PORTNUM_BASE(8'd0) + .PORTNUM_BASE(8'd0), + .RFNOC_PROTOVER(RFNOC_PROTOVER), + .NODE_INST_BASE(0) ) sfp_wrapper_0 ( .areset(global_rst), .gt_refclk(sfp0_gt_refclk), @@ -1843,7 +1847,7 @@ module n3xx ( // ////////////////////////////////////////////////////////////////////// - n3xx_mgt_channel_wrapper #( + n3xx_mgt_channel_wrapper #( .LANES(1), `ifdef SFP1_10GBE .PROTOCOL("10GbE"), @@ -1856,101 +1860,103 @@ module n3xx ( .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) .REG_AWIDTH(REG_AWIDTH), // Width of the address bus .GT_COMMON(1), - .PORTNUM_BASE(8'd1) - ) sfp_wrapper_1 ( - .areset(global_rst), + .PORTNUM_BASE(8'd1), + .RFNOC_PROTOVER(RFNOC_PROTOVER), + .NODE_INST_BASE(1) + ) sfp_wrapper_1 ( + .areset(global_rst), - .gt_refclk(sfp1_gt_refclk), - .gb_refclk(sfp1_gb_refclk), - .misc_clk(sfp1_misc_clk), - .user_clk(au_user_clk), - .sync_clk(au_sync_clk), - .gt_tx_out_clk_unbuf(sfp1_tx_out_clk), + .gt_refclk(sfp1_gt_refclk), + .gb_refclk(sfp1_gb_refclk), + .misc_clk(sfp1_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp1_tx_out_clk), - .bus_rst(bus_rst), - .bus_clk(bus_clk), + .bus_rst(bus_rst), + .bus_clk(bus_clk), - .qpllreset(qpllreset_sfp1), - .qplllock(qplllock), - .qplloutclk(qplloutclk), - .qplloutrefclk(qplloutrefclk), - .qpllrefclklost(), + .qpllreset(qpllreset_sfp1), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), - .mmcm_locked(au_mmcm_locked), - .gt_pll_lock(sfp1_gt_pll_lock), + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp1_gt_pll_lock), - .txp(SFP_1_TX_P), - .txn(SFP_1_TX_N), - .rxp(SFP_1_RX_P), - .rxn(SFP_1_RX_N), + .txp(SFP_1_TX_P), + .txn(SFP_1_TX_N), + .rxp(SFP_1_RX_P), + .rxn(SFP_1_RX_N), - .mod_rxlos(SFP_1_LOS), - .mod_tx_fault(SFP_1_TXFAULT), - .mod_tx_disable(SFP_1_TXDISABLE), + .mod_rxlos(SFP_1_LOS), + .mod_tx_fault(SFP_1_TXFAULT), + .mod_tx_disable(SFP_1_TXDISABLE), - // Clock and reset - .s_axi_aclk(clk40), - .s_axi_aresetn(clk40_rstn), - // AXI4-Lite: Write address port (domain: s_axi_aclk) - .s_axi_awaddr(M_AXI_NET1_AWADDR[REG_AWIDTH-1:0]), - .s_axi_awvalid(M_AXI_NET1_AWVALID), - .s_axi_awready(M_AXI_NET1_AWREADY), - // AXI4-Lite: Write data port (domain: s_axi_aclk) - .s_axi_wdata(M_AXI_NET1_WDATA), - .s_axi_wstrb(M_AXI_NET1_WSTRB), - .s_axi_wvalid(M_AXI_NET1_WVALID), - .s_axi_wready(M_AXI_NET1_WREADY), - // AXI4-Lite: Write response port (domain: s_axi_aclk) - .s_axi_bresp(M_AXI_NET1_BRESP), - .s_axi_bvalid(M_AXI_NET1_BVALID), - .s_axi_bready(M_AXI_NET1_BREADY), - // AXI4-Lite: Read address port (domain: s_axi_aclk) - .s_axi_araddr(M_AXI_NET1_ARADDR[REG_AWIDTH-1:0]), - .s_axi_arvalid(M_AXI_NET1_ARVALID), - .s_axi_arready(M_AXI_NET1_ARREADY), - // AXI4-Lite: Read data port (domain: s_axi_aclk) - .s_axi_rdata(M_AXI_NET1_RDATA), - .s_axi_rresp(M_AXI_NET1_RRESP), - .s_axi_rvalid(M_AXI_NET1_RVALID), - .s_axi_rready(M_AXI_NET1_RREADY), + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET1_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET1_AWVALID), + .s_axi_awready(M_AXI_NET1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET1_WDATA), + .s_axi_wstrb(M_AXI_NET1_WSTRB), + .s_axi_wvalid(M_AXI_NET1_WVALID), + .s_axi_wready(M_AXI_NET1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET1_BRESP), + .s_axi_bvalid(M_AXI_NET1_BVALID), + .s_axi_bready(M_AXI_NET1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET1_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET1_ARVALID), + .s_axi_arready(M_AXI_NET1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET1_RDATA), + .s_axi_rresp(M_AXI_NET1_RRESP), + .s_axi_rvalid(M_AXI_NET1_RVALID), + .s_axi_rready(M_AXI_NET1_RREADY), - // Ethernet to Vita - .e2v_tdata(e2v_sfp1_tdata), - .e2v_tlast(e2v_sfp1_tlast), - .e2v_tvalid(e2v_sfp1_tvalid), - .e2v_tready(e2v_sfp1_tready), + // Ethernet to Vita + .e2v_tdata(e2v_sfp1_tdata), + .e2v_tlast(e2v_sfp1_tlast), + .e2v_tvalid(e2v_sfp1_tvalid), + .e2v_tready(e2v_sfp1_tready), - // Vita to Ethernet - .v2e_tdata(v2e_sfp1_tdata), - .v2e_tlast(v2e_sfp1_tlast), - .v2e_tvalid(v2e_sfp1_tvalid), - .v2e_tready(v2e_sfp1_tready), + // Vita to Ethernet + .v2e_tdata(v2e_sfp1_tdata), + .v2e_tlast(v2e_sfp1_tlast), + .v2e_tvalid(v2e_sfp1_tvalid), + .v2e_tready(v2e_sfp1_tready), - // Ethernet to CPU - .e2c_tdata(arm_eth_sfp1_rx_tdata_b), - .e2c_tkeep(arm_eth_sfp1_rx_tkeep_b), - .e2c_tlast(arm_eth_sfp1_rx_tlast_b), - .e2c_tvalid(arm_eth_sfp1_rx_tvalid_b), - .e2c_tready(arm_eth_sfp1_rx_tready_b), + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp1_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp1_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp1_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp1_rx_tvalid_b), + .e2c_tready(arm_eth_sfp1_rx_tready_b), - // CPU to Ethernet - .c2e_tdata(arm_eth_sfp1_tx_tdata_b), - .c2e_tkeep(arm_eth_sfp1_tx_tkeep_b), - .c2e_tlast(arm_eth_sfp1_tx_tlast_b), - .c2e_tvalid(arm_eth_sfp1_tx_tvalid_b), - .c2e_tready(arm_eth_sfp1_tx_tready_b), + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp1_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp1_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp1_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp1_tx_tvalid_b), + .c2e_tready(arm_eth_sfp1_tx_tready_b), - // Misc - .port_info(sfp_port1_info), - .device_id(device_id), + // Misc + .port_info(sfp_port1_info), + .device_id(device_id), - // LED - .link_up(sfp1_link_up), - .activity(SFP_1_LED_A) - ); + // LED + .link_up(sfp1_link_up), + .activity(SFP_1_LED_A) + ); - assign ps_gpio_in[61] = ps_gpio_tri[61] ? sfp1_link_up : ps_gpio_out[61]; - assign SFP_1_LED_B = sfp1_link_up; + assign ps_gpio_in[61] = ps_gpio_tri[61] ? sfp1_link_up : ps_gpio_out[61]; + assign SFP_1_LED_B = sfp1_link_up; ///////////////////////////////////////////////////////////////////// // @@ -2567,7 +2573,9 @@ module n3xx ( eth_internal #( .DWIDTH(REG_DWIDTH), .AWIDTH(REG_AWIDTH), - .PORTNUM(8'd1) + .PORTNUM(8'd1), + .RFNOC_PROTOVER(RFNOC_PROTOVER), + .NODE_INST(2) ) eth_internal_i ( // Resets .bus_rst (bus_rst), diff --git a/top/n3xx/n3xx_mgt_channel_wrapper.v b/top/n3xx/n3xx_mgt_channel_wrapper.v index 6fc0470..d885828 100644 --- a/top/n3xx/n3xx_mgt_channel_wrapper.v +++ b/top/n3xx/n3xx_mgt_channel_wrapper.v @@ -1,27 +1,44 @@ -/////////////////////////////////////////////////////////////////// // -// Copyright 2018 Ettus Research, A National Instruments Company +// Copyright 2018 Ettus Research, a National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // // Module: n3xx_mgt_channel_wrapper +// // Description: +// // Aurora/10 GbE wrapper for up to 4 QSFP lanes -or- // Aurora/1 GbE/10 GbE/White Rabbit wrapper for 1 SFP+ lane // -////////////////////////////////////////////////////////////////////// +// Parameters: +// +// PROTOCOL : Must be {10GbE, Aurora, Disabled} +// LANES : Number of lanes of to instantiate (1, 2, 3, or 4) +// REG_BASE : Base register address +// PORTNUM_BASE : Base port number for discovery +// MDIO_EN : Enable MDIO port +// MDIO_PHYADDR : MDIO address to use +// REG_DWIDTH : Width of regport address bus +// REG_AWIDTH : Width of regport data bus +// GT_COMMON : Use GT Common ports on MGT +// RFNOC_PROTOVER : RFNoC protocol version to be reported by transport +// adapters. +// NODE_INST : RFNoC transport adapter node instance for this port +// `default_nettype none module n3xx_mgt_channel_wrapper #( - parameter PROTOCOL = "10GbE",// Must be {10GbE, Aurora, Disabled} - parameter LANES = 2, // Number of lanes of to instantiate (Supported = {1,2,3,4}) - parameter REG_BASE = 32'h0, // Base register address - parameter PORTNUM_BASE = 4, // Base port number for discovery - parameter MDIO_EN = 1, // Enable MDIO port - parameter [4:0] MDIO_PHYADDR = 5'd0, // Enable MDIO port - parameter REG_DWIDTH = 32, // Width of regport address bus - parameter REG_AWIDTH = 14, // Width of regport data bus - parameter GT_COMMON = 1 + parameter PROTOCOL = "10GbE", + parameter LANES = 2, + parameter REG_BASE = 32'h0, + parameter PORTNUM_BASE = 4, + parameter MDIO_EN = 1, + parameter [ 4:0] MDIO_PHYADDR = 5'd0, + parameter REG_DWIDTH = 32, + parameter REG_AWIDTH = 14, + parameter GT_COMMON = 1, + parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0}, + parameter NODE_INST_BASE = 0 )( // Resets input wire areset, @@ -268,14 +285,15 @@ module n3xx_mgt_channel_wrapper #( generate for (l = 0; l < LANES; l = l + 1) begin: lanes n3xx_mgt_wrapper #( - .PROTOCOL (PROTOCOL), - .REG_BASE (REG_BASE + (REG_BLOCK_SIZE * l)), - .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) - .REG_AWIDTH (REG_AWIDTH), // Width of the address bus - .GT_COMMON (GT_COMMON), - .MDIO_EN (MDIO_EN), - .MDIO_PHYADDR (MDIO_PHYADDR), - .PORTNUM (PORTNUM_BASE + l) + .PROTOCOL (PROTOCOL), + .REG_BASE (REG_BASE + (REG_BLOCK_SIZE * l)), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .GT_COMMON (GT_COMMON), + .MDIO_EN (MDIO_EN), + .MDIO_PHYADDR (MDIO_PHYADDR), + .PORTNUM (PORTNUM_BASE + l), + .NODE_INST (NODE_INST_BASE + l) ) lane_i ( //must reset all channels on quad when sfp1 gtx core is reset .areset (areset), diff --git a/top/n3xx/n3xx_mgt_wrapper.v b/top/n3xx/n3xx_mgt_wrapper.v index 0dc9eaf..28779e3 100644 --- a/top/n3xx/n3xx_mgt_wrapper.v +++ b/top/n3xx/n3xx_mgt_wrapper.v @@ -1,27 +1,48 @@ -/////////////////////////////////////////////////////////////////// // -// Copyright 2018 Ettus Research, A National Instruments Company +// Copyright 2018 Ettus Research, a National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // // Module: n3xx_mgt_wrapper -// Description: -// Provides wrapper for just the pieces specific to an MGT lane -// (for easy use with generate) // -////////////////////////////////////////////////////////////////////// +// Description: +// +// Wrapper for single MGT, including support for Aurora, WhiteRabbit, 10 GbE, +// and 1 GbE. +// +// Parameters: +// +// PROTOCOL : Must be "10GbE", "1GbE", "Aurora", or "Disabled". +// REG_DWIDTH : Data width of the AXI-Lite interface and RegPort +// REG_AWIDTH : Address width of the AXI-Lite interface and RegPort\ +// GT_COMMON : Use GT Common ports on MGT +// PORTNUM : Port number +// MDIO_EN : Enables internal MDIO master +// MDIO_PHYADDR : Address to use for the MDIO +// RFNOC_PROTOVER : RFNoC protocol version to be reported by transport +// adapters. +// NODE_INST : RFNoC transport adapter node instance for this port +// EN_RX_KV_MAP_CFG : Enable KV-map configuration port on transport adapter +// EN_RX_RAW_PYLD : Enable raw UDP support on transport adapter +// `default_nettype none + + module n3xx_mgt_wrapper #( - parameter PROTOCOL = "10GbE", // Must be {10GbE, Aurora, Disabled} - parameter REG_DWIDTH = 32, - parameter REG_AWIDTH = 14, - parameter GT_COMMON = 1, - parameter [7:0] PORTNUM = 8'd0, - parameter MDIO_EN = 0, - parameter [4:0] MDIO_PHYADDR = 5'd0, - parameter REG_BASE = 16'h0000 -)( + parameter PROTOCOL = "10GbE", + parameter REG_DWIDTH = 32, + parameter REG_AWIDTH = 14, + parameter REG_BASE = 16'h0000, + parameter GT_COMMON = 1, + parameter [ 7:0] PORTNUM = 8'd0, + parameter MDIO_EN = 0, + parameter [ 4:0] MDIO_PHYADDR = 5'd0, + parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0}, + parameter NODE_INST = 0, + parameter EN_RX_KV_MAP_CFG = 1, + parameter EN_RX_RAW_PYLD = 1 +) ( // Resets input wire areset, input wire bus_rst, @@ -378,13 +399,13 @@ module n3xx_mgt_wrapper #( // Converting tuser to tkeep for ingress packets assign e2c_tkeep = ~e2c_tlast ? 8'b1111_1111 - : (e2c_tuser == 4'd0) ? 8'b1111_1111 - : (e2c_tuser == 4'd1) ? 8'b0000_0001 - : (e2c_tuser == 4'd2) ? 8'b0000_0011 - : (e2c_tuser == 4'd3) ? 8'b0000_0111 - : (e2c_tuser == 4'd4) ? 8'b0000_1111 - : (e2c_tuser == 4'd5) ? 8'b0001_1111 - : (e2c_tuser == 4'd6) ? 8'b0011_1111 + : (e2c_tuser[2:0] == 3'd0) ? 8'b1111_1111 + : (e2c_tuser[2:0] == 3'd1) ? 8'b0000_0001 + : (e2c_tuser[2:0] == 3'd2) ? 8'b0000_0011 + : (e2c_tuser[2:0] == 3'd3) ? 8'b0000_0111 + : (e2c_tuser[2:0] == 3'd4) ? 8'b0000_1111 + : (e2c_tuser[2:0] == 3'd5) ? 8'b0001_1111 + : (e2c_tuser[2:0] == 3'd6) ? 8'b0011_1111 : 8'b0111_1111; // Converting tkeep to tuser for egress packets @@ -399,58 +420,120 @@ module n3xx_mgt_wrapper #( : (c2e_tkeep == 8'b0000_0001) ? 4'd1 : 4'd0; - eth_interface #( - .PROTOVER ({8'd1,8'd0}), //FIXME. This should come from outside - .MTU (10), - .NODE_INST (0), - .REG_AWIDTH (REG_AWIDTH), - .BASE (REG_BASE_ETH_SWITCH) - ) eth_interface ( - .clk (bus_clk), - .reset (bus_rst), - .device_id (device_id), - .reg_wr_req (reg_wr_req), - .reg_wr_addr (reg_wr_addr), - .reg_wr_data (reg_wr_data), - .reg_rd_req (reg_rd_req), - .reg_rd_addr (reg_rd_addr), - .reg_rd_resp (reg_rd_resp_eth_if), - .reg_rd_data (reg_rd_data_eth_if), - .my_mac (), - .my_ip (), - .my_udp_port (), - .eth_tx_tdata (mgti_tdata), - .eth_tx_tuser (mgti_tuser), - .eth_tx_tlast (mgti_tlast), - .eth_tx_tvalid (mgti_tvalid), - .eth_tx_tready (mgti_tready), - .eth_rx_tdata (mgto_tdata), - .eth_rx_tuser (mgto_tuser), - .eth_rx_tlast (mgto_tlast), - .eth_rx_tvalid (mgto_tvalid), - .eth_rx_tready (mgto_tready), - .e2v_tdata (e2v_tdata), - .e2v_tlast (e2v_tlast), - .e2v_tvalid (e2v_tvalid), - .e2v_tready (e2v_tready), - .v2e_tdata (v2e_tdata), - .v2e_tlast (v2e_tlast), - .v2e_tvalid (v2e_tvalid), - .v2e_tready (v2e_tready), - .e2c_tdata (e2c_tdata), - .e2c_tuser (e2c_tuser), - .e2c_tlast (e2c_tlast), - .e2c_tvalid (e2c_tvalid), - .e2c_tready (e2c_tready), - .c2e_tdata (c2e_tdata), - .c2e_tuser (c2e_tuser), - .c2e_tlast (c2e_tlast), - .c2e_tvalid (c2e_tvalid), - .c2e_tready (c2e_tready) - ); - + if (EN_RX_KV_MAP_CFG || EN_RX_RAW_PYLD) begin : gen_eth_ipv4_interface_wrapper + eth_ipv4_interface_wrapper #( + .PROTOVER (RFNOC_PROTOVER), + .NODE_INST (NODE_INST), + .REG_AWIDTH (REG_AWIDTH), + .BASE (REG_BASE_ETH_SWITCH), + .SYNC (1), + .EN_RX_KV_MAP_CFG (EN_RX_KV_MAP_CFG), + .EN_RX_RAW_PYLD (EN_RX_RAW_PYLD) + ) eth_ipv4_interface_wrapper_i ( + .bus_clk (bus_clk), + .bus_rst (bus_rst), + .device_id (device_id), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp_eth_if), + .reg_rd_data (reg_rd_data_eth_if), + .my_mac (), + .my_ip (), + .my_udp_chdr_port (), + .eth_clk (bus_clk), + .eth_rst (bus_rst), + .eth_pause_req (), + .eth_tx_tdata (mgti_tdata), + .eth_tx_tuser (mgti_tuser), + .eth_tx_tkeep (), + .eth_tx_tlast (mgti_tlast), + .eth_tx_tvalid (mgti_tvalid), + .eth_tx_tready (mgti_tready), + .eth_rx_tdata (mgto_tdata), + .eth_rx_tuser (mgto_tuser), + .eth_rx_tlast (mgto_tlast), + .eth_rx_tvalid (mgto_tvalid), + .eth_rx_tready (mgto_tready), + .e2v_tdata (e2v_tdata), + .e2v_tlast (e2v_tlast), + .e2v_tvalid (e2v_tvalid), + .e2v_tready (e2v_tready), + .v2e_tdata (v2e_tdata), + .v2e_tlast (v2e_tlast), + .v2e_tvalid (v2e_tvalid), + .v2e_tready (v2e_tready), + .cpu_clk (bus_clk), + .cpu_rst (bus_rst), + .e2c_tdata (e2c_tdata), + .e2c_tuser (e2c_tuser), + .e2c_tlast (e2c_tlast), + .e2c_tvalid (e2c_tvalid), + .e2c_tready (e2c_tready), + .c2e_tdata (c2e_tdata), + .c2e_tuser (c2e_tuser), + .c2e_tlast (c2e_tlast), + .c2e_tvalid (c2e_tvalid), + .c2e_tready (c2e_tready) + ); + end // gen_eth_ipv4_interface_wrapper + else begin : gen_eth_interface + eth_interface #( + .PROTOVER (RFNOC_PROTOVER), + .MTU (10), + .NODE_INST (NODE_INST), + .REG_AWIDTH (REG_AWIDTH), + .BASE (REG_BASE_ETH_SWITCH) + ) eth_interface ( + .clk (bus_clk), + .reset (bus_rst), + .device_id (device_id), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp_eth_if), + .reg_rd_data (reg_rd_data_eth_if), + .my_mac (), + .my_ip (), + .my_udp_port (), + .eth_tx_tdata (mgti_tdata), + .eth_tx_tuser (mgti_tuser), + .eth_tx_tlast (mgti_tlast), + .eth_tx_tvalid (mgti_tvalid), + .eth_tx_tready (mgti_tready), + .eth_rx_tdata (mgto_tdata), + .eth_rx_tuser (mgto_tuser), + .eth_rx_tlast (mgto_tlast), + .eth_rx_tvalid (mgto_tvalid), + .eth_rx_tready (mgto_tready), + .e2v_tdata (e2v_tdata), + .e2v_tlast (e2v_tlast), + .e2v_tvalid (e2v_tvalid), + .e2v_tready (e2v_tready), + .v2e_tdata (v2e_tdata), + .v2e_tlast (v2e_tlast), + .v2e_tvalid (v2e_tvalid), + .v2e_tready (v2e_tready), + .e2c_tdata (e2c_tdata), + .e2c_tuser (e2c_tuser), + .e2c_tlast (e2c_tlast), + .e2c_tvalid (e2c_tvalid), + .e2c_tready (e2c_tready), + .c2e_tdata (c2e_tdata), + .c2e_tuser (c2e_tuser), + .c2e_tlast (c2e_tlast), + .c2e_tvalid (c2e_tvalid), + .c2e_tready (c2e_tready) + ); + end // gen_eth_interface end endgenerate endmodule // n3xx_mgt_wrapper + + `default_nettype wire