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fpga: n3xx: Support advanced transport adapter

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- Fix NODE_INST
- Fix RFNOC_PROTOVER
- Add option to use SystemVerilog transport adapter for raw UDP


Original-commit: 693ec2c896306bcba3686385e5861593040d4cbd
This commit is contained in:
Wade Fife
2022-08-29 17:01:45 -05:00
committed by skooNI
parent 6981891978
commit a270cb29d6
5 changed files with 426 additions and 305 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/n3xx/dboards/mg/n3xx.v
+135 -127
View File
@@ -1178,7 +1178,9 @@ module n3xx (
.LANES (NUM_QSFP_LANES),
.PORTNUM_BASE (4),
.REG_DWIDTH (REG_DWIDTH),
.REG_AWIDTH (QSFP_REG_AWIDTH)
.REG_AWIDTH (QSFP_REG_AWIDTH),
.RFNOC_PROTOVER (RFNOC_PROTOVER),
.NODE_INST_BASE (0)
) qsfp_wrapper_i (
.areset (global_rst),
.gt_refclk (qsfp_gt_refclk),
@@ -1694,147 +1696,149 @@ module n3xx (
`endif
.REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
.REG_AWIDTH(REG_AWIDTH), // Width of the address bus
.PORTNUM_BASE(8'd0)
) sfp_wrapper_0 (
.areset(global_rst),
.gt_refclk(sfp0_gt_refclk),
.gb_refclk(sfp0_gb_refclk),
.misc_clk(sfp0_misc_clk),
.user_clk(au_user_clk),
.sync_clk(au_sync_clk),
.gt_tx_out_clk_unbuf(sfp0_tx_out_clk),
.PORTNUM_BASE(8'd0),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST_BASE(0)
) sfp_wrapper_0 (
.areset(global_rst),
.gt_refclk(sfp0_gt_refclk),
.gb_refclk(sfp0_gb_refclk),
.misc_clk(sfp0_misc_clk),
.user_clk(au_user_clk),
.sync_clk(au_sync_clk),
.gt_tx_out_clk_unbuf(sfp0_tx_out_clk),
.bus_rst(bus_rst),
.bus_clk(bus_clk),
.bus_rst(bus_rst),
.bus_clk(bus_clk),
.qpllreset(qpllreset_sfp0),
.qplllock(qplllock),
.qplloutclk(qplloutclk),
.qplloutrefclk(qplloutrefclk),
.qpllrefclklost(),
.qpllreset(qpllreset_sfp0),
.qplllock(qplllock),
.qplloutclk(qplloutclk),
.qplloutrefclk(qplloutrefclk),
.qpllrefclklost(),
.mmcm_locked(au_mmcm_locked),
.gt_pll_lock(sfp0_gt_pll_lock),
.mmcm_locked(au_mmcm_locked),
.gt_pll_lock(sfp0_gt_pll_lock),
.txp(SFP_0_TX_P),
.txn(SFP_0_TX_N),
.rxp(SFP_0_RX_P),
.rxn(SFP_0_RX_N),
.txp(SFP_0_TX_P),
.txn(SFP_0_TX_N),
.rxp(SFP_0_RX_P),
.rxn(SFP_0_RX_N),
.mod_present_n(SFP_0_I2C_NPRESENT),
.mod_rxlos(SFP_0_LOS),
.mod_tx_fault(SFP_0_TXFAULT),
.mod_tx_disable(SFP_0_TXDISABLE),
.mod_present_n(SFP_0_I2C_NPRESENT),
.mod_rxlos(SFP_0_LOS),
.mod_tx_fault(SFP_0_TXFAULT),
.mod_tx_disable(SFP_0_TXDISABLE),
// Clock and reset
.s_axi_aclk(clk40),
.s_axi_aresetn(clk40_rstn),
// AXI4-Lite: Write address port (domain: s_axi_aclk)
.s_axi_awaddr(M_AXI_NET0_AWADDR[REG_AWIDTH-1:0]),
.s_axi_awvalid(M_AXI_NET0_AWVALID),
.s_axi_awready(M_AXI_NET0_AWREADY),
// AXI4-Lite: Write data port (domain: s_axi_aclk)
.s_axi_wdata(M_AXI_NET0_WDATA),
.s_axi_wstrb(M_AXI_NET0_WSTRB),
.s_axi_wvalid(M_AXI_NET0_WVALID),
.s_axi_wready(M_AXI_NET0_WREADY),
// AXI4-Lite: Write response port (domain: s_axi_aclk)
.s_axi_bresp(M_AXI_NET0_BRESP),
.s_axi_bvalid(M_AXI_NET0_BVALID),
.s_axi_bready(M_AXI_NET0_BREADY),
// AXI4-Lite: Read address port (domain: s_axi_aclk)
.s_axi_araddr(M_AXI_NET0_ARADDR[REG_AWIDTH-1:0]),
.s_axi_arvalid(M_AXI_NET0_ARVALID),
.s_axi_arready(M_AXI_NET0_ARREADY),
// AXI4-Lite: Read data port (domain: s_axi_aclk)
.s_axi_rdata(M_AXI_NET0_RDATA),
.s_axi_rresp(M_AXI_NET0_RRESP),
.s_axi_rvalid(M_AXI_NET0_RVALID),
.s_axi_rready(M_AXI_NET0_RREADY),
// Clock and reset
.s_axi_aclk(clk40),
.s_axi_aresetn(clk40_rstn),
// AXI4-Lite: Write address port (domain: s_axi_aclk)
.s_axi_awaddr(M_AXI_NET0_AWADDR[REG_AWIDTH-1:0]),
.s_axi_awvalid(M_AXI_NET0_AWVALID),
.s_axi_awready(M_AXI_NET0_AWREADY),
// AXI4-Lite: Write data port (domain: s_axi_aclk)
.s_axi_wdata(M_AXI_NET0_WDATA),
.s_axi_wstrb(M_AXI_NET0_WSTRB),
.s_axi_wvalid(M_AXI_NET0_WVALID),
.s_axi_wready(M_AXI_NET0_WREADY),
// AXI4-Lite: Write response port (domain: s_axi_aclk)
.s_axi_bresp(M_AXI_NET0_BRESP),
.s_axi_bvalid(M_AXI_NET0_BVALID),
.s_axi_bready(M_AXI_NET0_BREADY),
// AXI4-Lite: Read address port (domain: s_axi_aclk)
.s_axi_araddr(M_AXI_NET0_ARADDR[REG_AWIDTH-1:0]),
.s_axi_arvalid(M_AXI_NET0_ARVALID),
.s_axi_arready(M_AXI_NET0_ARREADY),
// AXI4-Lite: Read data port (domain: s_axi_aclk)
.s_axi_rdata(M_AXI_NET0_RDATA),
.s_axi_rresp(M_AXI_NET0_RRESP),
.s_axi_rvalid(M_AXI_NET0_RVALID),
.s_axi_rready(M_AXI_NET0_RREADY),
// Ethernet to Vita
.e2v_tdata(e2v_sfp0_tdata),
.e2v_tlast(e2v_sfp0_tlast),
.e2v_tvalid(e2v_sfp0_tvalid),
.e2v_tready(e2v_sfp0_tready),
// Ethernet to Vita
.e2v_tdata(e2v_sfp0_tdata),
.e2v_tlast(e2v_sfp0_tlast),
.e2v_tvalid(e2v_sfp0_tvalid),
.e2v_tready(e2v_sfp0_tready),
// Vita to Ethernet
.v2e_tdata(v2e_sfp0_tdata),
.v2e_tlast(v2e_sfp0_tlast),
.v2e_tvalid(v2e_sfp0_tvalid),
.v2e_tready(v2e_sfp0_tready),
// Vita to Ethernet
.v2e_tdata(v2e_sfp0_tdata),
.v2e_tlast(v2e_sfp0_tlast),
.v2e_tvalid(v2e_sfp0_tvalid),
.v2e_tready(v2e_sfp0_tready),
// Ethernet to CPU
.e2c_tdata(arm_eth_sfp0_rx_tdata_b),
.e2c_tkeep(arm_eth_sfp0_rx_tkeep_b),
.e2c_tlast(arm_eth_sfp0_rx_tlast_b),
.e2c_tvalid(arm_eth_sfp0_rx_tvalid_b),
.e2c_tready(arm_eth_sfp0_rx_tready_b),
// Ethernet to CPU
.e2c_tdata(arm_eth_sfp0_rx_tdata_b),
.e2c_tkeep(arm_eth_sfp0_rx_tkeep_b),
.e2c_tlast(arm_eth_sfp0_rx_tlast_b),
.e2c_tvalid(arm_eth_sfp0_rx_tvalid_b),
.e2c_tready(arm_eth_sfp0_rx_tready_b),
// CPU to Ethernet
.c2e_tdata(arm_eth_sfp0_tx_tdata_b),
.c2e_tkeep(arm_eth_sfp0_tx_tkeep_b),
.c2e_tlast(arm_eth_sfp0_tx_tlast_b),
.c2e_tvalid(arm_eth_sfp0_tx_tvalid_b),
.c2e_tready(arm_eth_sfp0_tx_tready_b),
// CPU to Ethernet
.c2e_tdata(arm_eth_sfp0_tx_tdata_b),
.c2e_tkeep(arm_eth_sfp0_tx_tkeep_b),
.c2e_tlast(arm_eth_sfp0_tx_tlast_b),
.c2e_tvalid(arm_eth_sfp0_tx_tvalid_b),
.c2e_tready(arm_eth_sfp0_tx_tready_b),
// White Rabbit Specific
// White Rabbit Specific
`ifdef SFP0_WR
.wr_reset_n (~ps_gpio_out[48]), // reset for WR only
.wr_refclk (wr_refclk_buf),
.wr_dac_sclk (WB_DAC_SCLK),
.wr_dac_din (WB_DAC_DIN),
.wr_dac_clr_n (WB_DAC_NCLR),
.wr_dac_cs_n (WB_DAC_NSYNC),
.wr_dac_ldac_n(WB_DAC_NLDAC),
.wr_eeprom_scl_o(), // storage for delay characterization
.wr_eeprom_scl_i(1'b0), // temp
.wr_eeprom_sda_o(),
.wr_eeprom_sda_i(1'b0), // temp
.wr_uart_rx(wr_uart_rxd), // to/from PS
.wr_uart_tx(wr_uart_txd),
.mod_pps(pps_wr_refclk), // out, reference clock and pps
.mod_refclk(wr_ref_clk),
// WR Slave Port to PS
.wr_axi_aclk(m_axi_wr_clk), // out to PS
.wr_axi_aresetn(1'b1), // in
.wr_axi_awaddr(m_axi_wr_awaddr),
.wr_axi_awvalid(m_axi_wr_awvalid),
.wr_axi_awready(m_axi_wr_awready),
.wr_axi_wdata(m_axi_wr_wdata),
.wr_axi_wstrb(m_axi_wr_wstrb),
.wr_axi_wvalid(m_axi_wr_wvalid),
.wr_axi_wready(m_axi_wr_wready),
.wr_axi_bresp(m_axi_wr_bresp),
.wr_axi_bvalid(m_axi_wr_bvalid),
.wr_axi_bready(m_axi_wr_bready),
.wr_axi_araddr(m_axi_wr_araddr),
.wr_axi_arvalid(m_axi_wr_arvalid),
.wr_axi_arready(m_axi_wr_arready),
.wr_axi_rdata(m_axi_wr_rdata),
.wr_axi_rresp(m_axi_wr_rresp),
.wr_axi_rvalid(m_axi_wr_rvalid),
.wr_axi_rready(m_axi_wr_rready),
.wr_axi_rlast(),
.wr_reset_n (~ps_gpio_out[48]), // reset for WR only
.wr_refclk (wr_refclk_buf),
.wr_dac_sclk (WB_DAC_SCLK),
.wr_dac_din (WB_DAC_DIN),
.wr_dac_clr_n (WB_DAC_NCLR),
.wr_dac_cs_n (WB_DAC_NSYNC),
.wr_dac_ldac_n(WB_DAC_NLDAC),
.wr_eeprom_scl_o(), // storage for delay characterization
.wr_eeprom_scl_i(1'b0), // temp
.wr_eeprom_sda_o(),
.wr_eeprom_sda_i(1'b0), // temp
.wr_uart_rx(wr_uart_rxd), // to/from PS
.wr_uart_tx(wr_uart_txd),
.mod_pps(pps_wr_refclk), // out, reference clock and pps
.mod_refclk(wr_ref_clk),
// WR Slave Port to PS
.wr_axi_aclk(m_axi_wr_clk), // out to PS
.wr_axi_aresetn(1'b1), // in
.wr_axi_awaddr(m_axi_wr_awaddr),
.wr_axi_awvalid(m_axi_wr_awvalid),
.wr_axi_awready(m_axi_wr_awready),
.wr_axi_wdata(m_axi_wr_wdata),
.wr_axi_wstrb(m_axi_wr_wstrb),
.wr_axi_wvalid(m_axi_wr_wvalid),
.wr_axi_wready(m_axi_wr_wready),
.wr_axi_bresp(m_axi_wr_bresp),
.wr_axi_bvalid(m_axi_wr_bvalid),
.wr_axi_bready(m_axi_wr_bready),
.wr_axi_araddr(m_axi_wr_araddr),
.wr_axi_arvalid(m_axi_wr_arvalid),
.wr_axi_arready(m_axi_wr_arready),
.wr_axi_rdata(m_axi_wr_rdata),
.wr_axi_rresp(m_axi_wr_rresp),
.wr_axi_rvalid(m_axi_wr_rvalid),
.wr_axi_rready(m_axi_wr_rready),
.wr_axi_rlast(),
`else
.wr_reset_n(1'b1),
.wr_refclk(1'b0),
.wr_eeprom_scl_i(1'b0),
.wr_eeprom_sda_i(1'b0),
.wr_uart_rx(1'b0),
.wr_reset_n(1'b1),
.wr_refclk(1'b0),
.wr_eeprom_scl_i(1'b0),
.wr_eeprom_sda_i(1'b0),
.wr_uart_rx(1'b0),
`endif
// Misc
.port_info(sfp_port0_info),
.device_id(device_id),
// Misc
.port_info(sfp_port0_info),
.device_id(device_id),
// LED
.link_up(sfp0_link_up),
.activity(SFP_0_LED_A)
);
// LED
.link_up(sfp0_link_up),
.activity(SFP_0_LED_A)
);
assign ps_gpio_in[60] = ps_gpio_tri[60] ? sfp0_link_up : ps_gpio_out[60];
assign SFP_0_LED_B = sfp0_link_up;
assign ps_gpio_in[60] = ps_gpio_tri[60] ? sfp0_link_up : ps_gpio_out[60];
assign SFP_0_LED_B = sfp0_link_up;
`ifndef SFP0_WR
assign WB_DAC_SCLK = 1'b0;
@@ -1865,7 +1869,9 @@ module n3xx (
`endif
.REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
.REG_AWIDTH(REG_AWIDTH), // Width of the address bus
.PORTNUM_BASE(8'd1)
.PORTNUM_BASE(8'd1),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST_BASE(1)
) sfp_wrapper_1 (
.areset(global_rst),
@@ -2576,7 +2582,9 @@ module n3xx (
eth_internal #(
.DWIDTH(REG_DWIDTH),
.AWIDTH(REG_AWIDTH),
.PORTNUM(8'd1)
.PORTNUM(8'd1),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST(2)
) eth_internal_i (
// Resets
.bus_rst (bus_rst),
top/n3xx/dboards/rh/n3xx.v
+93 -85
View File
@@ -1168,7 +1168,9 @@ module n3xx (
.GT_COMMON (1),
.PORTNUM_BASE (4),
.REG_DWIDTH (REG_DWIDTH),
.REG_AWIDTH (QSFP_REG_AWIDTH)
.REG_AWIDTH (QSFP_REG_AWIDTH),
.RFNOC_PROTOVER (RFNOC_PROTOVER),
.NODE_INST_BASE (0)
) qsfp_wrapper_i (
.areset (global_rst),
.gt_refclk (qsfp_gt_refclk),
@@ -1685,7 +1687,9 @@ module n3xx (
.REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
.REG_AWIDTH(REG_AWIDTH), // Width of the address bus
.GT_COMMON(1),
.PORTNUM_BASE(8'd0)
.PORTNUM_BASE(8'd0),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST_BASE(0)
) sfp_wrapper_0 (
.areset(global_rst),
.gt_refclk(sfp0_gt_refclk),
@@ -1843,7 +1847,7 @@ module n3xx (
//
//////////////////////////////////////////////////////////////////////
n3xx_mgt_channel_wrapper #(
n3xx_mgt_channel_wrapper #(
.LANES(1),
`ifdef SFP1_10GBE
.PROTOCOL("10GbE"),
@@ -1856,101 +1860,103 @@ module n3xx (
.REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
.REG_AWIDTH(REG_AWIDTH), // Width of the address bus
.GT_COMMON(1),
.PORTNUM_BASE(8'd1)
) sfp_wrapper_1 (
.areset(global_rst),
.PORTNUM_BASE(8'd1),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST_BASE(1)
) sfp_wrapper_1 (
.areset(global_rst),
.gt_refclk(sfp1_gt_refclk),
.gb_refclk(sfp1_gb_refclk),
.misc_clk(sfp1_misc_clk),
.user_clk(au_user_clk),
.sync_clk(au_sync_clk),
.gt_tx_out_clk_unbuf(sfp1_tx_out_clk),
.gt_refclk(sfp1_gt_refclk),
.gb_refclk(sfp1_gb_refclk),
.misc_clk(sfp1_misc_clk),
.user_clk(au_user_clk),
.sync_clk(au_sync_clk),
.gt_tx_out_clk_unbuf(sfp1_tx_out_clk),
.bus_rst(bus_rst),
.bus_clk(bus_clk),
.bus_rst(bus_rst),
.bus_clk(bus_clk),
.qpllreset(qpllreset_sfp1),
.qplllock(qplllock),
.qplloutclk(qplloutclk),
.qplloutrefclk(qplloutrefclk),
.qpllrefclklost(),
.qpllreset(qpllreset_sfp1),
.qplllock(qplllock),
.qplloutclk(qplloutclk),
.qplloutrefclk(qplloutrefclk),
.qpllrefclklost(),
.mmcm_locked(au_mmcm_locked),
.gt_pll_lock(sfp1_gt_pll_lock),
.mmcm_locked(au_mmcm_locked),
.gt_pll_lock(sfp1_gt_pll_lock),
.txp(SFP_1_TX_P),
.txn(SFP_1_TX_N),
.rxp(SFP_1_RX_P),
.rxn(SFP_1_RX_N),
.txp(SFP_1_TX_P),
.txn(SFP_1_TX_N),
.rxp(SFP_1_RX_P),
.rxn(SFP_1_RX_N),
.mod_rxlos(SFP_1_LOS),
.mod_tx_fault(SFP_1_TXFAULT),
.mod_tx_disable(SFP_1_TXDISABLE),
.mod_rxlos(SFP_1_LOS),
.mod_tx_fault(SFP_1_TXFAULT),
.mod_tx_disable(SFP_1_TXDISABLE),
// Clock and reset
.s_axi_aclk(clk40),
.s_axi_aresetn(clk40_rstn),
// AXI4-Lite: Write address port (domain: s_axi_aclk)
.s_axi_awaddr(M_AXI_NET1_AWADDR[REG_AWIDTH-1:0]),
.s_axi_awvalid(M_AXI_NET1_AWVALID),
.s_axi_awready(M_AXI_NET1_AWREADY),
// AXI4-Lite: Write data port (domain: s_axi_aclk)
.s_axi_wdata(M_AXI_NET1_WDATA),
.s_axi_wstrb(M_AXI_NET1_WSTRB),
.s_axi_wvalid(M_AXI_NET1_WVALID),
.s_axi_wready(M_AXI_NET1_WREADY),
// AXI4-Lite: Write response port (domain: s_axi_aclk)
.s_axi_bresp(M_AXI_NET1_BRESP),
.s_axi_bvalid(M_AXI_NET1_BVALID),
.s_axi_bready(M_AXI_NET1_BREADY),
// AXI4-Lite: Read address port (domain: s_axi_aclk)
.s_axi_araddr(M_AXI_NET1_ARADDR[REG_AWIDTH-1:0]),
.s_axi_arvalid(M_AXI_NET1_ARVALID),
.s_axi_arready(M_AXI_NET1_ARREADY),
// AXI4-Lite: Read data port (domain: s_axi_aclk)
.s_axi_rdata(M_AXI_NET1_RDATA),
.s_axi_rresp(M_AXI_NET1_RRESP),
.s_axi_rvalid(M_AXI_NET1_RVALID),
.s_axi_rready(M_AXI_NET1_RREADY),
// Clock and reset
.s_axi_aclk(clk40),
.s_axi_aresetn(clk40_rstn),
// AXI4-Lite: Write address port (domain: s_axi_aclk)
.s_axi_awaddr(M_AXI_NET1_AWADDR[REG_AWIDTH-1:0]),
.s_axi_awvalid(M_AXI_NET1_AWVALID),
.s_axi_awready(M_AXI_NET1_AWREADY),
// AXI4-Lite: Write data port (domain: s_axi_aclk)
.s_axi_wdata(M_AXI_NET1_WDATA),
.s_axi_wstrb(M_AXI_NET1_WSTRB),
.s_axi_wvalid(M_AXI_NET1_WVALID),
.s_axi_wready(M_AXI_NET1_WREADY),
// AXI4-Lite: Write response port (domain: s_axi_aclk)
.s_axi_bresp(M_AXI_NET1_BRESP),
.s_axi_bvalid(M_AXI_NET1_BVALID),
.s_axi_bready(M_AXI_NET1_BREADY),
// AXI4-Lite: Read address port (domain: s_axi_aclk)
.s_axi_araddr(M_AXI_NET1_ARADDR[REG_AWIDTH-1:0]),
.s_axi_arvalid(M_AXI_NET1_ARVALID),
.s_axi_arready(M_AXI_NET1_ARREADY),
// AXI4-Lite: Read data port (domain: s_axi_aclk)
.s_axi_rdata(M_AXI_NET1_RDATA),
.s_axi_rresp(M_AXI_NET1_RRESP),
.s_axi_rvalid(M_AXI_NET1_RVALID),
.s_axi_rready(M_AXI_NET1_RREADY),
// Ethernet to Vita
.e2v_tdata(e2v_sfp1_tdata),
.e2v_tlast(e2v_sfp1_tlast),
.e2v_tvalid(e2v_sfp1_tvalid),
.e2v_tready(e2v_sfp1_tready),
// Ethernet to Vita
.e2v_tdata(e2v_sfp1_tdata),
.e2v_tlast(e2v_sfp1_tlast),
.e2v_tvalid(e2v_sfp1_tvalid),
.e2v_tready(e2v_sfp1_tready),
// Vita to Ethernet
.v2e_tdata(v2e_sfp1_tdata),
.v2e_tlast(v2e_sfp1_tlast),
.v2e_tvalid(v2e_sfp1_tvalid),
.v2e_tready(v2e_sfp1_tready),
// Vita to Ethernet
.v2e_tdata(v2e_sfp1_tdata),
.v2e_tlast(v2e_sfp1_tlast),
.v2e_tvalid(v2e_sfp1_tvalid),
.v2e_tready(v2e_sfp1_tready),
// Ethernet to CPU
.e2c_tdata(arm_eth_sfp1_rx_tdata_b),
.e2c_tkeep(arm_eth_sfp1_rx_tkeep_b),
.e2c_tlast(arm_eth_sfp1_rx_tlast_b),
.e2c_tvalid(arm_eth_sfp1_rx_tvalid_b),
.e2c_tready(arm_eth_sfp1_rx_tready_b),
// Ethernet to CPU
.e2c_tdata(arm_eth_sfp1_rx_tdata_b),
.e2c_tkeep(arm_eth_sfp1_rx_tkeep_b),
.e2c_tlast(arm_eth_sfp1_rx_tlast_b),
.e2c_tvalid(arm_eth_sfp1_rx_tvalid_b),
.e2c_tready(arm_eth_sfp1_rx_tready_b),
// CPU to Ethernet
.c2e_tdata(arm_eth_sfp1_tx_tdata_b),
.c2e_tkeep(arm_eth_sfp1_tx_tkeep_b),
.c2e_tlast(arm_eth_sfp1_tx_tlast_b),
.c2e_tvalid(arm_eth_sfp1_tx_tvalid_b),
.c2e_tready(arm_eth_sfp1_tx_tready_b),
// CPU to Ethernet
.c2e_tdata(arm_eth_sfp1_tx_tdata_b),
.c2e_tkeep(arm_eth_sfp1_tx_tkeep_b),
.c2e_tlast(arm_eth_sfp1_tx_tlast_b),
.c2e_tvalid(arm_eth_sfp1_tx_tvalid_b),
.c2e_tready(arm_eth_sfp1_tx_tready_b),
// Misc
.port_info(sfp_port1_info),
.device_id(device_id),
// Misc
.port_info(sfp_port1_info),
.device_id(device_id),
// LED
.link_up(sfp1_link_up),
.activity(SFP_1_LED_A)
);
// LED
.link_up(sfp1_link_up),
.activity(SFP_1_LED_A)
);
assign ps_gpio_in[61] = ps_gpio_tri[61] ? sfp1_link_up : ps_gpio_out[61];
assign SFP_1_LED_B = sfp1_link_up;
assign ps_gpio_in[61] = ps_gpio_tri[61] ? sfp1_link_up : ps_gpio_out[61];
assign SFP_1_LED_B = sfp1_link_up;
/////////////////////////////////////////////////////////////////////
//
@@ -2567,7 +2573,9 @@ module n3xx (
eth_internal #(
.DWIDTH(REG_DWIDTH),
.AWIDTH(REG_AWIDTH),
.PORTNUM(8'd1)
.PORTNUM(8'd1),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST(2)
) eth_internal_i (
// Resets
.bus_rst (bus_rst),