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fpga: x400: zbx: Add support for ZBX CPLD

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Co-authored-by: Cherwa Vang <cherwa.vang@ni.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>


Original-commit: 99b841c75aa91709090cbf4046bf51b7ffb4f612
This commit is contained in:
Javier Valenzuela
2021-06-10 11:56:58 -05:00
committed by Aaron Rossetto
co-authored by Cherwa Vang Martin Braun Max Köhler Paul Butler
parent 7e59e9516d
commit a1d7c252c2
37 changed files with 17727 additions and 0 deletions
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top/x400/dboards/zbx/cpld/ip/osc/osc.qsys
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<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element int_osc_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10M04SAU324I7G" />
<parameter name="deviceFamily" value="MAX 10" />
<parameter name="deviceSpeedGrade" value="7" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clkout" internal="int_osc_0.clkout" type="clock" dir="start">
<port name="clkout" internal="clkout" />
</interface>
<interface name="oscena" internal="int_osc_0.oscena" type="conduit" dir="end">
<port name="oscena" internal="oscena" />
</interface>
<module
name="int_osc_0"
kind="altera_int_osc"
version="18.1"
enabled="1"
autoexport="1">
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
<parameter name="CLOCK_FREQUENCY_1" value="55" />
<parameter name="CLOCK_FREQUENCY_2" value="77" />
<parameter name="DEVICE_FAMILY" value="MAX 10" />
<parameter name="PART_NAME" value="10M04SAU324I7G" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>