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fpga: lib: Fix Vivado warnings

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Original-commit: ad3d614426e068a067692df411412ce3ed936c39
This commit is contained in:
Wade Fife
2023-06-09 09:01:04 -05:00
parent 0817f084a3
commit 9ed8bb22d6
9 changed files with 19 additions and 14 deletions
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lib/rfnoc/core/axis_data_to_chdr.v
+2
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@@ -501,6 +501,8 @@ module axis_data_to_chdr #(
end
always @(*) begin
// Initialize to 0 to avoid latch on unassigned bits
chdr_pf_tdata = {CHDR_W{1'b0}};
case (state)
ST_HDR: begin
// Insert header word
lib/rfnoc/crossbar/chdr_crossbar_nxn.v
+3 -3
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@@ -341,7 +341,7 @@ module chdr_crossbar_nxn #(
.s_axis_chdr_tvalid (s_axis_tvalid[n] ),
.s_axis_chdr_tready (s_axis_tready[n] ),
.s_axis_chdr_tuser (1'd0 ),
.m_axis_chdr_tdata (i_tdata [n] ),
.m_axis_chdr_tdata (i_tdata [n][CHDR_W(n)-1:0] ),
.m_axis_chdr_tdest (i_tdest [n] ),
.m_axis_chdr_tid (i_tid [n] ),
.m_axis_chdr_tlast (i_tlast [n] ),
@@ -386,13 +386,13 @@ module chdr_crossbar_nxn #(
) chdr_xb_ingress_buff_i (
.clk (clk ),
.reset (reset ),
.s_axis_chdr_tdata (i_tdata [n] ),
.s_axis_chdr_tdata (i_tdata [n][CHDR_W(n)-1:0] ),
.s_axis_chdr_tdest (i_tdest [n][NPORTS_W-1:0] ),
.s_axis_chdr_tid (i_tid [n] ),
.s_axis_chdr_tlast (i_tlast [n] ),
.s_axis_chdr_tvalid (i_tvalid [n] ),
.s_axis_chdr_tready (i_tready [n] ),
.m_axis_chdr_tdata (buf_tdata [n] ),
.m_axis_chdr_tdata (buf_tdata [n][CHDR_W(n)-1:0] ),
.m_axis_chdr_tdest (buf_tdest_tmp[n] ),
.m_axis_chdr_tkeep (buf_tkeep [n] ),
.m_axis_chdr_tlast (buf_tlast [n] ),
lib/rfnoc/crossbar/gen_node_to_coord_mapping.py
+1 -1
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@@ -106,7 +106,7 @@ def gen_vheader(dimsize, mapgen, pattern, filename):
vhfile.write('//\n')
vhfile.write('// Autogenerated file. Do not modify.\n')
vhfile.write('// $ %s\n'%(' '.join(sys.argv[:])))
vhfile.write('\nparameter CLOG2_DIM_SIZE = $clog2(DIM_SIZE); //Vivado workaround\n\n')
vhfile.write('\nlocalparam CLOG2_DIM_SIZE = $clog2(DIM_SIZE); //Vivado workaround\n\n')
for i in range(2, dimsize+1):
nodes = mapgen(i)
N = math.sqrt(len(nodes))
lib/rfnoc/crossbar/mesh_node_mapping.vh
+1 -1
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@@ -4,7 +4,7 @@
// Autogenerated file. Do not modify.
// $ ./gen_node_to_coord_mapping.py --dimsize 16 --pattern spiral
parameter CLOG2_DIM_SIZE = $clog2(DIM_SIZE); //Vivado workaround
localparam CLOG2_DIM_SIZE = $clog2(DIM_SIZE); //Vivado workaround
// DIM_SIZE = 2, PATTERN = SPIRAL
lib/rfnoc/dds_freq_tune_duc.v
+1 -1
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@@ -125,7 +125,7 @@ module dds_freq_tune_duc #(
// Width of each component of the DDS output. This width is fixed by the IP
// configuration.
parameter DDS_W = 16;
localparam DDS_W = 16;
wire m_axis_dds_tlast;
wire m_axis_dds_tvalid;
lib/rfnoc/xport_sv/eth_ipv4_internal.sv
+1
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@@ -351,6 +351,7 @@ module eth_ipv4_internal #(
.CPU_FIFO_SIZE (BYTE_MTU),
.CHDR_FIFO_SIZE (BYTE_MTU),
.NODE_INST (NODE_INST),
.REG_AWIDTH (AWIDTH),
.BASE (REG_BASE_ETH_SWITCH),
.PREAMBLE_BYTES (6),
.ADD_SOF (1),