diff --git a/lib/axi/axis_data_swap.v b/lib/axi/axis_data_swap.v index 2408ab6..3b15b5f 100644 --- a/lib/axi/axis_data_swap.v +++ b/lib/axi/axis_data_swap.v @@ -51,8 +51,8 @@ module axis_data_swap #( input wire m_axis_tready ); - parameter SWAP_STAGES = $clog2(DATA_W); - parameter SWAP_W = $clog2(DATA_W)-1; + localparam SWAP_STAGES = $clog2(DATA_W); + localparam SWAP_W = $clog2(DATA_W)-1; genvar s, w; wire [DATA_W-1:0] stg_tdata [0:SWAP_STAGES], stg_tdata_swp[0:SWAP_STAGES], stg_tdata_res[0:SWAP_STAGES]; diff --git a/lib/axi4s_sv/axi4s_packet_gate.sv b/lib/axi4s_sv/axi4s_packet_gate.sv index a6d190d..54cd883 100644 --- a/lib/axi4s_sv/axi4s_packet_gate.sv +++ b/lib/axi4s_sv/axi4s_packet_gate.sv @@ -26,8 +26,8 @@ module axi4s_packet_gate #( ) ( input logic clear=1'b0, input logic error=1'b0, - interface i, // AxiStreamIf or AxiStreamPacketIf - interface o // AxiStreamIf or AxiStreamPacketIf + interface.slave i, // AxiStreamIf or AxiStreamPacketIf + interface.master o // AxiStreamIf or AxiStreamPacketIf ); `include "axi4s.vh" diff --git a/lib/control/map/cam_priority_encoder.v b/lib/control/map/cam_priority_encoder.v index 5125134..1c2d4d9 100644 --- a/lib/control/map/cam_priority_encoder.v +++ b/lib/control/map/cam_priority_encoder.v @@ -43,8 +43,8 @@ module cam_priority_encoder # ); // power-of-two width -parameter W1 = 2**$clog2(WIDTH); -parameter W2 = W1/2; +localparam W1 = 2**$clog2(WIDTH); +localparam W2 = W1/2; generate if (WIDTH == 2) begin @@ -67,7 +67,8 @@ generate priority_encoder_inst1 ( .input_unencoded(input_unencoded[W2-1:0]), .output_valid(valid1), - .output_encoded(out1) + .output_encoded(out1), + .output_unencoded() ); cam_priority_encoder #( .WIDTH(W2), @@ -76,7 +77,8 @@ generate priority_encoder_inst2 ( .input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}), .output_valid(valid2), - .output_encoded(out2) + .output_encoded(out2), + .output_unencoded() ); // multiplexer to select part assign output_valid = valid1 | valid2; diff --git a/lib/rfnoc/core/axis_data_to_chdr.v b/lib/rfnoc/core/axis_data_to_chdr.v index fe149e1..d6b0a4d 100644 --- a/lib/rfnoc/core/axis_data_to_chdr.v +++ b/lib/rfnoc/core/axis_data_to_chdr.v @@ -501,6 +501,8 @@ module axis_data_to_chdr #( end always @(*) begin + // Initialize to 0 to avoid latch on unassigned bits + chdr_pf_tdata = {CHDR_W{1'b0}}; case (state) ST_HDR: begin // Insert header word diff --git a/lib/rfnoc/crossbar/chdr_crossbar_nxn.v b/lib/rfnoc/crossbar/chdr_crossbar_nxn.v index 8be3b30..dd843dc 100644 --- a/lib/rfnoc/crossbar/chdr_crossbar_nxn.v +++ b/lib/rfnoc/crossbar/chdr_crossbar_nxn.v @@ -341,7 +341,7 @@ module chdr_crossbar_nxn #( .s_axis_chdr_tvalid (s_axis_tvalid[n] ), .s_axis_chdr_tready (s_axis_tready[n] ), .s_axis_chdr_tuser (1'd0 ), - .m_axis_chdr_tdata (i_tdata [n] ), + .m_axis_chdr_tdata (i_tdata [n][CHDR_W(n)-1:0] ), .m_axis_chdr_tdest (i_tdest [n] ), .m_axis_chdr_tid (i_tid [n] ), .m_axis_chdr_tlast (i_tlast [n] ), @@ -386,13 +386,13 @@ module chdr_crossbar_nxn #( ) chdr_xb_ingress_buff_i ( .clk (clk ), .reset (reset ), - .s_axis_chdr_tdata (i_tdata [n] ), + .s_axis_chdr_tdata (i_tdata [n][CHDR_W(n)-1:0] ), .s_axis_chdr_tdest (i_tdest [n][NPORTS_W-1:0] ), .s_axis_chdr_tid (i_tid [n] ), .s_axis_chdr_tlast (i_tlast [n] ), .s_axis_chdr_tvalid (i_tvalid [n] ), .s_axis_chdr_tready (i_tready [n] ), - .m_axis_chdr_tdata (buf_tdata [n] ), + .m_axis_chdr_tdata (buf_tdata [n][CHDR_W(n)-1:0] ), .m_axis_chdr_tdest (buf_tdest_tmp[n] ), .m_axis_chdr_tkeep (buf_tkeep [n] ), .m_axis_chdr_tlast (buf_tlast [n] ), diff --git a/lib/rfnoc/crossbar/gen_node_to_coord_mapping.py b/lib/rfnoc/crossbar/gen_node_to_coord_mapping.py index a2eaf71..dff0661 100755 --- a/lib/rfnoc/crossbar/gen_node_to_coord_mapping.py +++ b/lib/rfnoc/crossbar/gen_node_to_coord_mapping.py @@ -106,7 +106,7 @@ def gen_vheader(dimsize, mapgen, pattern, filename): vhfile.write('//\n') vhfile.write('// Autogenerated file. Do not modify.\n') vhfile.write('// $ %s\n'%(' '.join(sys.argv[:]))) - vhfile.write('\nparameter CLOG2_DIM_SIZE = $clog2(DIM_SIZE); //Vivado workaround\n\n') + vhfile.write('\nlocalparam CLOG2_DIM_SIZE = $clog2(DIM_SIZE); //Vivado workaround\n\n') for i in range(2, dimsize+1): nodes = mapgen(i) N = math.sqrt(len(nodes)) diff --git a/lib/rfnoc/crossbar/mesh_node_mapping.vh b/lib/rfnoc/crossbar/mesh_node_mapping.vh index 466b0c6..de8b367 100644 --- a/lib/rfnoc/crossbar/mesh_node_mapping.vh +++ b/lib/rfnoc/crossbar/mesh_node_mapping.vh @@ -4,7 +4,7 @@ // Autogenerated file. Do not modify. // $ ./gen_node_to_coord_mapping.py --dimsize 16 --pattern spiral -parameter CLOG2_DIM_SIZE = $clog2(DIM_SIZE); //Vivado workaround +localparam CLOG2_DIM_SIZE = $clog2(DIM_SIZE); //Vivado workaround // DIM_SIZE = 2, PATTERN = SPIRAL diff --git a/lib/rfnoc/dds_freq_tune_duc.v b/lib/rfnoc/dds_freq_tune_duc.v index 4b8a299..889cbaa 100644 --- a/lib/rfnoc/dds_freq_tune_duc.v +++ b/lib/rfnoc/dds_freq_tune_duc.v @@ -125,7 +125,7 @@ module dds_freq_tune_duc #( // Width of each component of the DDS output. This width is fixed by the IP // configuration. - parameter DDS_W = 16; + localparam DDS_W = 16; wire m_axis_dds_tlast; wire m_axis_dds_tvalid; diff --git a/lib/rfnoc/xport_sv/eth_ipv4_internal.sv b/lib/rfnoc/xport_sv/eth_ipv4_internal.sv index 1851ef2..52ddc1e 100644 --- a/lib/rfnoc/xport_sv/eth_ipv4_internal.sv +++ b/lib/rfnoc/xport_sv/eth_ipv4_internal.sv @@ -351,6 +351,7 @@ module eth_ipv4_internal #( .CPU_FIFO_SIZE (BYTE_MTU), .CHDR_FIFO_SIZE (BYTE_MTU), .NODE_INST (NODE_INST), + .REG_AWIDTH (AWIDTH), .BASE (REG_BASE_ETH_SWITCH), .PREAMBLE_BYTES (6), .ADD_SOF (1),