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fpga: lib: Fix axi_packet_gate RAM dib width

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Original-commit: ed1b58053c53bfbd3f3b667a0ebe0aa8066e2b0e
This commit is contained in:
Wade Fife
2020-06-29 13:41:15 -05:00
committed by Aaron Rossetto
parent 9b0e42678f
commit 9e0f859bb6
1 changed files with 1 additions and 1 deletions
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lib/fifo/axi_packet_gate.v
+1 -1
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@@ -70,7 +70,7 @@ module axi_packet_gate #(
.clka (clk), .ena(1'b1), .wea(wr_en), .clka (clk), .ena(1'b1), .wea(wr_en),
.addra(wr_addr), .dia(wr_data), .doa(), .addra(wr_addr), .dia(wr_data), .doa(),
.clkb (clk), .enb(rd_en), .web(1'b0), .clkb (clk), .enb(rd_en), .web(1'b0),
.addrb(rd_addr), .dib({WIDTH{1'b0}}), .dob(rd_data) .addrb(rd_addr), .dib({WIDTH+1{1'b0}}), .dob(rd_data)
); );
// FIFO empty/full logic. The condition for both // FIFO empty/full logic. The condition for both