miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: Fix errors found by linting with vsim

Browse Source 
Original-commit: 5c7237fb407cfccaee205980d97e40ce10768c2a
This commit is contained in:
Andrew Moch
2020-03-23 08:23:51 -05:00
committed by Wade Fife
parent 09751b661e
commit 97dcb5363d
6 changed files with 22 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv
+2 -4
View File
@@ -36,8 +36,7 @@ module cap_pattern_verifier_tb();
.PATTERN("RAMP"),
.RAMP_START(14'h0000),
.RAMP_STOP(14'h3FFF),
.RAMP_INCR(14'h0001),
.NTH_CYCLE(1)
.RAMP_INCR(14'h0001)
) dut0 (
.clk(clk),
.rst(rst),
@@ -54,8 +53,7 @@ module cap_pattern_verifier_tb();
.PATTERN("RAMP"),
.RAMP_START(14'h0100),
.RAMP_STOP(14'h0FFF),
.RAMP_INCR(14'h0001),
.NTH_CYCLE(1)
.RAMP_INCR(14'h0001)
) dut1 (
.clk(clk),
.rst(rst),