miegl/b210-k7-fpga
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fpga: Fix errors found by linting with vsim

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Original-commit: 5c7237fb407cfccaee205980d97e40ce10768c2a
This commit is contained in:
Andrew Moch authored and Wade Fife committed 2020-03-23 08:23:51 -05:00
1 parent 09751b661e
commit 97dcb5363d
6 files changed
+22 -19
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lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv
+2 -4
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@@ -36,8 +36,7 @@ module cap_pattern_verifier_tb();
.PATTERN("RAMP"),
.RAMP_START(14'h0000),
.RAMP_STOP(14'h3FFF),
.RAMP_INCR(14'h0001),
.NTH_CYCLE(1)
.RAMP_INCR(14'h0001)
) dut0 (
.clk(clk),
.rst(rst),
@@ -54,8 +53,7 @@ module cap_pattern_verifier_tb();
.PATTERN("RAMP"),
.RAMP_START(14'h0100),
.RAMP_STOP(14'h0FFF),
.RAMP_INCR(14'h0001),
.NTH_CYCLE(1)
.RAMP_INCR(14'h0001)
) dut1 (
.clk(clk),
.rst(rst),