fpga: Fix errors found by linting with vsim

Original-commit: 5c7237fb407cfccaee205980d97e40ce10768c2a
2020-03-23 08:23:51 -05:00
parent 09751b661e
commit 97dcb5363d
6 changed files with 22 additions and 19 deletions
@@ -35,7 +35,6 @@ module file_source #(
    end
  end

-  wire [31:0] sid;
  reg  [11:0] seqnum;
  wire [15:0] rate;
  reg  [1:0]  state;