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fpga: x400: Add GPIO control via ATR and DB state

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Original-commit: 9335939b9b3ab85cee5908ff3357f9e7819e3366
This commit is contained in:
Javier Valenzuela
2022-01-25 10:18:47 -07:00
committed by Wade Fife
parent 4edae39d9e
commit 962d01e583
14 changed files with 2934 additions and 201 deletions
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top/x400/x4xx_core.v
+2 -1
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@@ -241,7 +241,6 @@ module x4xx_core #(
wire [ 2*NUM_DBOARDS-1:0] ctrlport_radio_resp_status;
wire [ 32*NUM_DBOARDS-1:0] ctrlport_radio_resp_data;
x4xx_core_common #(
.CHDR_CLK_RATE (CHDR_CLK_RATE),
.CHDR_W (CHDR_W),
@@ -318,6 +317,8 @@ module x4xx_core #(
.nco_reset_done (nco_reset_done),
.adc_reset_pulse (adc_reset_pulse),
.dac_reset_pulse (dac_reset_pulse),
.tx_running (tx_running),
.rx_running (rx_running),
.qsfp_port_0_0_info (qsfp_port_0_0_info),
.qsfp_port_0_1_info (qsfp_port_0_1_info),
.qsfp_port_0_2_info (qsfp_port_0_2_info),