+
+Window to access the DIO register map through the control port from the radio blocks.
- 554176790
+ 554243347
- 0x21081116
+ 0x21091513
diff --git a/top/x400/doc/x4xx_core_common_buses.svg b/top/x400/doc/x4xx_core_common_buses.svg
new file mode 100644
index 0000000..6dafbfe
--- /dev/null
+++ b/top/x400/doc/x4xx_core_common_buses.svg
@@ -0,0 +1,3 @@
+
+
+s_radio_ctrlport_*[1:0] rfdc_timing_control ctrlport_decoder_param rf_ctrlport m_radio_ctrlport_*[1:0] gpio_atr_ctrlport radio_dio x4xx_gpio_atr_i x4xx_gpio_spi_wrapper_i ctrlport_combiner
ctrlport_combiner... dio_ctrlport windowed_mpm_dio x4xx_dio ctrlport_decoder_param
ctrlport_decoder_param... ctrlport_clk_cross
ctrlport_clk_cross... mpm_dio_* ctrlport_splitter m_* ctrlport_clk_cross s_ctrlport timekeeper_* versioning_* global_regs_* dio_* x4xx_global_regs x4xx_versioning_regs timekeeper From AXI From Radio One Instance Per Daghterboard
One Instance Per Dag... To Daughterboards gpio_spi_ctrlport Viewer does not support full SVG 1.1
// Each radio's CtrlPort peripheral interface is divided into the
// following memory spaces. Note that the CtrlPort peripheral interface
-// starts at offset 0x80000 in the RFNoC Radio block's register space.
+// starts at offset 0x80000 in the RFNoC Radio block's register space.
+// The following diagram displays the distribution of the CtrlPort
+// interface to the different modules it interacts with.
+//
// Daughterboard GPIO interface. Register access within this space
// is directed to the associated daughterboard CPLD.
@@ -637,8 +723,9 @@ endmodule
//
// RFDC timing control interface.
//
-//
-// DIO control interface
+//
+// DIO control interface. Interacts with the DIO source selection
+// block, ATR-based DIO control and the DIO digital interface
//
//
//
@@ -651,6 +738,10 @@ endmodule
// The registers contained here conform the mboard-regs node that MPM uses
// to manage general FPGA control/status calls, such as versioning,
// timekeeper, GPIO, etc.
+//
+// The following diagram shows how the communication bus interacts with the
+// modules in CORE_REGS.
+//
//
@@ -662,9 +753,25 @@ endmodule
//
// Window to access the timekeeper register map.
//
-//
+//
// Window to access the DIO register map.
//
//
//
+
+//
+//
+// This map contains register windows for controlling the different sources
+// that drive the state of DIO lines.
+//
+//
+//
+// Contains controls for DIO behavior based on the ATR state of the accessed radio
+//
+//
+// Window to access the DIO register map through the control port from the radio blocks.
+//
+//
+//
+
//XmlParse xml_off
diff --git a/top/x400/x4xx_dio.v b/top/x400/x4xx_dio.v
index 871a239..b67ecfa 100644
--- a/top/x400/x4xx_dio.v
+++ b/top/x400/x4xx_dio.v
@@ -9,10 +9,23 @@
//
// This module contains the motherboard registers for the DIO
// auxiliary board and the logic to drive these GPIO signals.
+// Arbitration between different sources to control the state
+// of the GPIO lines includes support for the following sources:
+// - s_ctrlport_* (combination of CtrlPort from PS AXI and radio blocks)
+// - PS dio control from Processing System's GPIOs
+// - ATR state (up to two DBs)
+// - User Application
+// - radio-controlled digital bus interface
+// For a visual representation of how the different sources are
+// arbitrated, as well as representation on what each source control
+// register refers to, please refer to the "Front-Panel Programmable
+// GPIOs" section of the USRP Manual.
//
// Parameters:
//
-// REG_BASE : Base address to use for registers.
+// REG_BASE : Base address to use for registers.
+// REG_SIZE : Register space size.
+// NUM_DBOARDS : Number of daughterboards to support.
//
`default_nettype none
@@ -20,7 +33,8 @@
module x4xx_dio #(
parameter REG_BASE = 0,
- parameter REG_SIZE = 'h20
+ parameter REG_SIZE = 'h30,
+ parameter NUM_DBOARDS = 2
) (
// Slave ctrlport interface
input wire ctrlport_clk,
@@ -43,11 +57,31 @@ module x4xx_dio #(
output wire [11:0] gpio_out_a,
output wire [11:0] gpio_out_b,
- // GPIO to application (async)
- output wire [11:0] gpio_in_fabric_a,
- output wire [11:0] gpio_in_fabric_b,
- input wire [11:0] gpio_out_fabric_a,
- input wire [11:0] gpio_out_fabric_b
+ // ATR GPIO Control (ctrlport_clk)
+ input wire [NUM_DBOARDS*32-1:0] atr_gpio_out,
+ input wire [NUM_DBOARDS*32-1:0] atr_gpio_ddr,
+
+ // PS GPIO Control from Block Design (async)
+ input wire [31:0] ps_gpio_out,
+ input wire [31:0] ps_gpio_ddr,
+
+ // Digital Interface Control (ctrlport_clk)
+ input wire [31:0] digital_ifc_gpio_out_radio0,
+ input wire [31:0] digital_ifc_gpio_ddr_radio0,
+ input wire [31:0] digital_ifc_gpio_out_radio1,
+ input wire [31:0] digital_ifc_gpio_ddr_radio1,
+
+ // GPIO to user application (async)
+ // User application relies on the local direction register
+ // for GPIO direction control. For this reason, we skip
+ // a mux to select between the user application and the
+ // local register direction control in the mux chain, and
+ // propagate their shared direction(from the local register)
+ // to the remainder of the mux chain.
+ output wire [11:0] user_app_in_a,
+ output wire [11:0] user_app_in_b,
+ input wire [11:0] user_app_out_a,
+ input wire [11:0] user_app_out_b
);
`include "../../lib/rfnoc/core/ctrlport.vh"
@@ -70,6 +104,16 @@ module x4xx_dio #(
reg [DIO_WIDTH-1:0] dio_master_b = {DIO_WIDTH {1'b0}};
reg [DIO_WIDTH-1:0] dio_output_a = {DIO_WIDTH {1'b0}};
reg [DIO_WIDTH-1:0] dio_output_b = {DIO_WIDTH {1'b0}};
+ reg [DIO_WIDTH-1:0] dio_source_a = {DIO_WIDTH {1'b0}};
+ reg [DIO_WIDTH-1:0] dio_source_b = {DIO_WIDTH {1'b0}};
+ reg [DIO_WIDTH-1:0] dio_radio_a = {DIO_WIDTH {1'b0}};
+ reg [DIO_WIDTH-1:0] dio_radio_b = {DIO_WIDTH {1'b0}};
+ reg [DIO_WIDTH-1:0] dio_interface_a = {DIO_WIDTH {1'b0}};
+ reg [DIO_WIDTH-1:0] dio_interface_b = {DIO_WIDTH {1'b0}};
+ reg [DIO_WIDTH-1:0] dio_override_a = {DIO_WIDTH {1'b0}};
+ reg [DIO_WIDTH-1:0] dio_override_b = {DIO_WIDTH {1'b0}};
+ reg [DIO_WIDTH-1:0] dio_sw_ctrl_a = {DIO_WIDTH {1'b0}};
+ reg [DIO_WIDTH-1:0] dio_sw_ctrl_b = {DIO_WIDTH {1'b0}};
wire [DIO_WIDTH-1:0] dio_input_a;
wire [DIO_WIDTH-1:0] dio_input_b;
@@ -93,6 +137,16 @@ module x4xx_dio #(
dio_master_b <= {DIO_WIDTH {1'b0}};
dio_output_a <= {DIO_WIDTH {1'b0}};
dio_output_b <= {DIO_WIDTH {1'b0}};
+ dio_source_a <= {DIO_WIDTH {1'b0}};
+ dio_source_b <= {DIO_WIDTH {1'b0}};
+ dio_radio_a <= {DIO_WIDTH {1'b0}};
+ dio_radio_b <= {DIO_WIDTH {1'b0}};
+ dio_interface_a <= {DIO_WIDTH {1'b0}};
+ dio_interface_b <= {DIO_WIDTH {1'b0}};
+ dio_override_a <= {DIO_WIDTH {1'b0}};
+ dio_override_b <= {DIO_WIDTH {1'b0}};
+ dio_sw_ctrl_a <= {DIO_WIDTH {1'b0}};
+ dio_sw_ctrl_b <= {DIO_WIDTH {1'b0}};
end else begin
// Write registers
@@ -104,18 +158,43 @@ module x4xx_dio #(
case (s_ctrlport_req_addr)
REG_BASE + DIO_MASTER_REGISTER: begin
- dio_master_a <= s_ctrlport_req_data[DIO_MASTER_A_MSB:DIO_MASTER_A];
- dio_master_b <= s_ctrlport_req_data[DIO_MASTER_B_MSB:DIO_MASTER_B];
+ dio_master_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
+ dio_master_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
end
REG_BASE + DIO_DIRECTION_REGISTER: begin
- dio_direction_a <= s_ctrlport_req_data[DIO_DIRECTION_A_MSB:DIO_DIRECTION_A];
- dio_direction_b <= s_ctrlport_req_data[DIO_DIRECTION_B_MSB:DIO_DIRECTION_B];
+ dio_direction_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
+ dio_direction_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
end
REG_BASE + DIO_OUTPUT_REGISTER: begin
- dio_output_a <= s_ctrlport_req_data[DIO_OUTPUT_A_MSB:DIO_OUTPUT_A];
- dio_output_b <= s_ctrlport_req_data[DIO_OUTPUT_B_MSB:DIO_OUTPUT_B];
+ dio_output_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
+ dio_output_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
+ end
+
+ REG_BASE + DIO_SOURCE_REGISTER: begin
+ dio_source_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
+ dio_source_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
+ end
+
+ REG_BASE + RADIO_SOURCE_REGISTER: begin
+ dio_radio_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
+ dio_radio_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
+ end
+
+ REG_BASE + INTERFACE_DIO_SELECT: begin
+ dio_interface_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
+ dio_interface_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
+ end
+
+ REG_BASE + DIO_OVERRIDE: begin
+ dio_override_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
+ dio_override_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
+ end
+
+ REG_BASE + SW_DIO_CONTROL: begin
+ dio_sw_ctrl_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
+ dio_sw_ctrl_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
end
// No register implementation for provided address
@@ -131,6 +210,7 @@ module x4xx_dio #(
end
endcase
+
// Read registers
end else if (s_ctrlport_req_rd) begin
// Acknowledge by default
@@ -140,23 +220,48 @@ module x4xx_dio #(
case (s_ctrlport_req_addr)
REG_BASE + DIO_MASTER_REGISTER: begin
- s_ctrlport_resp_data[DIO_MASTER_A_MSB:DIO_MASTER_A] <= dio_master_a;
- s_ctrlport_resp_data[DIO_MASTER_B_MSB:DIO_MASTER_B] <= dio_master_b;
+ s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_master_a;
+ s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_master_b;
end
REG_BASE + DIO_DIRECTION_REGISTER: begin
- s_ctrlport_resp_data[DIO_DIRECTION_A_MSB:DIO_DIRECTION_A] <= dio_direction_a;
- s_ctrlport_resp_data[DIO_DIRECTION_B_MSB:DIO_DIRECTION_B] <= dio_direction_b;
+ s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_direction_a;
+ s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_direction_b;
end
REG_BASE + DIO_OUTPUT_REGISTER: begin
- s_ctrlport_resp_data[DIO_OUTPUT_A_MSB:DIO_OUTPUT_A] <= dio_output_a;
- s_ctrlport_resp_data[DIO_OUTPUT_B_MSB:DIO_OUTPUT_B] <= dio_output_b;
+ s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_output_a;
+ s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_output_b;
end
REG_BASE + DIO_INPUT_REGISTER: begin
- s_ctrlport_resp_data[DIO_INPUT_A_MSB:DIO_INPUT_A] <= dio_input_a;
- s_ctrlport_resp_data[DIO_INPUT_B_MSB:DIO_INPUT_B] <= dio_input_b;
+ s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_input_a;
+ s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_input_b;
+ end
+
+ REG_BASE + DIO_SOURCE_REGISTER: begin
+ s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_source_a;
+ s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_source_b;
+ end
+
+ REG_BASE + RADIO_SOURCE_REGISTER: begin
+ s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_radio_a;
+ s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_radio_b;
+ end
+
+ REG_BASE + INTERFACE_DIO_SELECT: begin
+ s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_interface_a;
+ s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_interface_b;
+ end
+
+ REG_BASE + DIO_OVERRIDE: begin
+ s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_override_a;
+ s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_override_b;
+ end
+
+ REG_BASE + SW_DIO_CONTROL: begin
+ s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_sw_ctrl_a;
+ s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_sw_ctrl_b;
end
// No register implementation for provided address
@@ -198,31 +303,205 @@ module x4xx_dio #(
);
// Forward raw input to user application
- assign gpio_in_fabric_a = gpio_in_a;
- assign gpio_in_fabric_b = gpio_in_b;
+ assign user_app_in_a = gpio_in_a;
+ assign user_app_in_b = gpio_in_b;
- // Direction control
- assign gpio_en_a = dio_direction_a;
- assign gpio_en_b = dio_direction_b;
+ wire [DIO_WIDTH-1:0] gpio_out_sw_a;
+ wire [DIO_WIDTH-1:0] gpio_out_sw_b;
// Output assignment depending on master
generate
genvar i;
for (i = 0; i < DIO_WIDTH; i = i + 1) begin: dio_output_gen
- glitch_free_mux glitch_free_mux_dio_a (
+
+ reg atr_gpio_src_out_a_reg = 1'b0;
+ reg atr_gpio_src_out_b_reg = 1'b0;
+ reg atr_gpio_src_ddr_a_reg = 1'b0;
+ reg atr_gpio_src_ddr_b_reg = 1'b0;
+
+ // 1) Select which radio drives the output
+ always @ (posedge ctrlport_clk) begin
+ if (ctrlport_rst) begin
+ atr_gpio_src_out_a_reg <= 1'b0;
+ atr_gpio_src_out_b_reg <= 1'b0;
+ end else begin
+ atr_gpio_src_out_a_reg <= atr_gpio_out[dio_radio_a[i]*32 + DIO_PORT_A + i];
+ atr_gpio_src_out_b_reg <= atr_gpio_out[dio_radio_b[i]*32 + DIO_PORT_B + i];
+ end
+ end
+
+ // 2) Select which radio drives the direction
+ always @ (posedge ctrlport_clk) begin
+ if (ctrlport_rst) begin
+ atr_gpio_src_ddr_a_reg <= 1'b0;
+ atr_gpio_src_ddr_b_reg <= 1'b0;
+ end else begin
+ atr_gpio_src_ddr_a_reg <= atr_gpio_ddr[dio_radio_a[i]*32 + DIO_PORT_A + i];
+ atr_gpio_src_ddr_b_reg <= atr_gpio_ddr[dio_radio_b[i]*32 + DIO_PORT_B + i];
+ end
+ end
+
+ // Select between the Digital Interface in each radio(INTERFACE_DIO_SELECT)
+ wire dio_interface_mux_out_a;
+ wire dio_interface_mux_out_b;
+ wire dio_interface_mux_ddr_a;
+ wire dio_interface_mux_ddr_b;
+
+ glitch_free_mux glitch_free_interface_out_mux_dio_a (
+ .select (dio_interface_a[i]),
+ .signal0 (digital_ifc_gpio_out_radio0[DIO_PORT_A + i]),
+ .signal1 (digital_ifc_gpio_out_radio1[DIO_PORT_A + i]),
+ .muxed_signal (dio_interface_mux_out_a)
+ );
+
+ glitch_free_mux glitch_free_interface_out_mux_dio_b (
+ .select (dio_interface_b[i]),
+ .signal0 (digital_ifc_gpio_out_radio0[DIO_PORT_B + i]),
+ .signal1 (digital_ifc_gpio_out_radio1[DIO_PORT_B + i]),
+ .muxed_signal (dio_interface_mux_out_b)
+ );
+
+ glitch_free_mux glitch_free_interface_ddr_mux_dio_a (
+ .select (dio_interface_a[i]),
+ .signal0 (digital_ifc_gpio_ddr_radio0[DIO_PORT_A + i]),
+ .signal1 (digital_ifc_gpio_ddr_radio1[DIO_PORT_A + i]),
+ .muxed_signal (dio_interface_mux_ddr_a)
+ );
+
+ glitch_free_mux glitch_free_interface_ddr_mux_dio_b (
+ .select (dio_interface_b[i]),
+ .signal0 (digital_ifc_gpio_ddr_radio0[DIO_PORT_B + i]),
+ .signal1 (digital_ifc_gpio_ddr_radio1[DIO_PORT_B + i]),
+ .muxed_signal (dio_interface_mux_ddr_b)
+ );
+
+
+ // Select between ATR or Digital control(DIO_OVERRIDE)
+ wire dio_override_mux_out_a;
+ wire dio_override_mux_out_b;
+ wire dio_override_mux_ddr_a;
+ wire dio_override_mux_ddr_b;
+
+ glitch_free_mux glitch_free_override_out_mux_dio_a (
+ .select (dio_override_a[i]),
+ .signal0 (atr_gpio_src_out_a_reg),
+ .signal1 (dio_interface_mux_out_a),
+ .muxed_signal (dio_override_mux_out_a)
+ );
+
+ glitch_free_mux glitch_free_override_out_mux_dio_b (
+ .select (dio_override_b[i]),
+ .signal0 (atr_gpio_src_out_b_reg),
+ .signal1 (dio_interface_mux_out_b),
+ .muxed_signal (dio_override_mux_out_b)
+ );
+
+ glitch_free_mux glitch_free_override_ddr_mux_dio_a (
+ .select (dio_override_a[i]),
+ .signal0 (atr_gpio_src_ddr_a_reg),
+ .signal1 (dio_interface_mux_ddr_a),
+ .muxed_signal (dio_override_mux_ddr_a)
+ );
+
+ glitch_free_mux glitch_free_override_ddr_mux_dio_b (
+ .select (dio_override_b[i]),
+ .signal0 (atr_gpio_src_ddr_b_reg),
+ .signal1 (dio_interface_mux_ddr_b),
+ .muxed_signal (dio_override_mux_ddr_b)
+ );
+
+
+ // SW source select
+ // SW_DIO_CONTROL, select between PS and local register
+
+ wire dio_sw_control_mux_out_a;
+ wire dio_sw_control_mux_out_b;
+ wire dio_sw_control_mux_ddr_a;
+ wire dio_sw_control_mux_ddr_b;
+
+ glitch_free_mux glitch_free_sw_control_out_mux_dio_a (
+ .select (dio_sw_ctrl_a[i]),
+ .signal0 (dio_output_a[i]),
+ .signal1 (ps_gpio_out[DIO_PORT_A + i]),
+ .muxed_signal (dio_sw_control_mux_out_a)
+ );
+
+ glitch_free_mux glitch_free_sw_control_out_mux_dio_b (
+ .select (dio_sw_ctrl_b[i]),
+ .signal0 (dio_output_b[i]),
+ .signal1 (ps_gpio_out[DIO_PORT_B + i]),
+ .muxed_signal (dio_sw_control_mux_out_b)
+ );
+
+ glitch_free_mux glitch_free_sw_control_ddr_mux_dio_a (
+ .select (dio_sw_ctrl_a[i]),
+ .signal0 (dio_direction_a[i]),
+ .signal1 (ps_gpio_ddr[DIO_PORT_A + i]),
+ .muxed_signal (dio_sw_control_mux_ddr_a)
+ );
+
+ glitch_free_mux glitch_free_sw_control_ddr_mux_dio_b (
+ .select (dio_sw_ctrl_b[i]),
+ .signal0 (dio_direction_b[i]),
+ .signal1 (ps_gpio_ddr[DIO_PORT_B + i]),
+ .muxed_signal (dio_sw_control_mux_ddr_b)
+ );
+
+
+ // DIO_MASTER_REGISTER Mux, select between SW_DIO_CONTROL
+ // and user application
+ // User application relies on the local direction register
+ // for GPIO direction control. For this reason, we skip
+ // a mux to select between the user application and the
+ // local register direction control in the mux chain, and
+ // propagate their shared direction(from the local register)
+ // to the remainder of the mux chain.
+ glitch_free_mux glitch_free_master_mux_dio_a (
.select (dio_master_a[i]),
- .signal0 (gpio_out_fabric_a[i]),
- .signal1 (dio_output_a[i]),
+ .signal0 (user_app_out_a[i]),
+ .signal1 (dio_sw_control_mux_out_a),
+ .muxed_signal (gpio_out_sw_a[i])
+ );
+
+ glitch_free_mux glitch_free_master_mux_dio_b (
+ .select (dio_master_b[i]),
+ .signal0 (user_app_out_b[i]),
+ .signal1 (dio_sw_control_mux_out_b),
+ .muxed_signal (gpio_out_sw_b[i])
+ );
+
+ // DIO_SOURCE_REGISTER mux, select between (DIO_MASTER_REGISTER output) and
+ // radio controlled source (DIO_OVERRIDE output).
+ glitch_free_mux glitch_free_source_out_mux_dio_a (
+ .select (dio_source_a[i]),
+ .signal0 (gpio_out_sw_a[i]),
+ .signal1 (dio_override_mux_out_a),
.muxed_signal (gpio_out_a[i])
);
- glitch_free_mux glitch_free_mux_dio_b (
- .select (dio_master_b[i]),
- .signal0 (gpio_out_fabric_b[i]),
- .signal1 (dio_output_b[i]),
+ glitch_free_mux glitch_free_source_out_mux_dio_b (
+ .select (dio_source_b[i]),
+ .signal0 (gpio_out_sw_b[i]),
+ .signal1 (dio_override_mux_out_b),
.muxed_signal (gpio_out_b[i])
);
+
+ // Direction control
+ glitch_free_mux glitch_free_dir_mux_dio_a (
+ .select (dio_source_a[i]),
+ .signal0 (dio_sw_control_mux_ddr_a),
+ .signal1 (dio_override_mux_ddr_a),
+ .muxed_signal (gpio_en_a[i])
+ );
+
+ glitch_free_mux glitch_free_dir_mux_dio_b (
+ .select (dio_source_b[i]),
+ .signal0 (dio_sw_control_mux_ddr_b),
+ .signal1 (dio_override_mux_ddr_b),
+ .muxed_signal (gpio_en_b[i])
+ );
end
+
endgenerate
endmodule
@@ -232,44 +511,90 @@ endmodule
//XmlParse xml_on
-//
+//
//
//
-// Registers to control the GPIO buffer direction on the FPGA connected to the DIO board.
-// Further registers enable the PS to control and read the GPIO lines as master.
-// Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers.
-// Set the DIO registers in @.PS_CPLD_BASE_REGMAP appropriately.
+// Registers to control the GPIO buffer direction on the FPGA connected to
+// the DIO board. Further registers enable different sources to control and
+// read the GPIO lines as master. The following diagram shows how source
+// selection multiplexers are arranged, as well as an indicator for the
+// register that control them.
+//
//
-//
+//
//
-// Sets whether the DIO signal line is driven by this register interface or the user application.{br/}
-// 0 = user application is master, 1 = PS is master
+// Holds a single bit setting for DIO lines in both ports. One bit per pin.
+//
+//
+//
+//
+//
+// Sets whether the DIO signal line is driven by this register interface
+// or the user application.{br/}
+// 0 = user application is master, 1 = output of @.SW_DIO_CONTROL is master
//
-//
-//
+//
//
// Set the direction of FPGA buffer connected to DIO ports on the DIO board.{br/}
-// Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA.
+// Each bit represents one signal line. 0 = line is an input to the FPGA,
+// 1 = line is an output driven by the FPGA.
//
-//
-//
+//
//
// Status of each bit at the FPGA input.
//
-//
-//
+//
//
-// Controls the values on each DIO signal line in case the line master is set to PS in @.DIO_MASTER_REGISTER.
+// Controls the values on each DIO signal line in case the line master is
+// set to PS in @.DIO_MASTER_REGISTER.
+//
+//
+//
+//
+// Controls whether the DIO lines reflect the state of @.DIO_MASTER_REGISTER
+// or the radio blocks. 0 = @.DIO_MASTER_REGISTER,
+// 1 = Radio block output(@.DIO_OVERRIDE)
+//
+//
+//
+//
+// Controls which radio block to use the ATR state from to determine the
+// state of the DIO lines.
+// 0 = Radio#0
+// 1 = Radio#1
+//
+//
+//
+//
+// Controls which of the two available digital interfaces controls the DIO lines.
+// 0 = Digital interface from Radio#0,
+// 1 = Digital Interface from Radio#1.
+//
+//
+//
+//
+// Controls whether the radio input to the @.DIO_SOURCE_REGISTER mux
+// connects to the ATR control or a Digital interface block. The output
+// of the mux controlled by this bit goes to @.DIO_SOURCE_REGISTER.
+// 0 = Drive the ATR state(@.RADIO_SOURCE_REGISTER), 1 = Drive
+// Digital interface block(Output of @.INTERFACE_DIO_SELECT).
+//
+//
+//
+//
+// Controls which source is forwarded to the @.DIO_MASTER_REGISTER mux.
+// This configuration is applied independently for each DIO line.
+// 0 = MPM Ctrlport endpoint, 1 = PS Netlist DIO signal.
//
-//
//
//
diff --git a/top/x400/x4xx_gpio_atr.v b/top/x400/x4xx_gpio_atr.v
new file mode 100644
index 0000000..98ba881
--- /dev/null
+++ b/top/x400/x4xx_gpio_atr.v
@@ -0,0 +1,376 @@
+//
+// Copyright 2021 Ettus Research, A National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: x4xx_gpio_atr
+//
+// Description:
+//
+// This module controls the behavior of a GPIO bus of arbitrary width
+// based on the current ATR state. The radio state is determined by
+// combining the TX and RX states of each rf channel in the radio in
+// the following order: {tx_rf1, rx_rf1, tx_rf0, rx_rf0}
+//
+// Parameters:
+//
+// REG_BASE : Base address to use for registers.
+// REG_SIZE : Register space size.
+// WIDTH : Number of GPIO lines controlled by this block.
+//
+module x4xx_gpio_atr #(
+ parameter REG_BASE = 0,
+ parameter REG_SIZE = 'h20,
+ parameter WIDTH = 32
+) (
+ // Slave ctrlport interface
+ input wire ctrlport_clk,
+ input wire ctrlport_rst,
+ input wire s_ctrlport_req_wr,
+ input wire s_ctrlport_req_rd,
+ input wire [19:0] s_ctrlport_req_addr,
+ input wire [31:0] s_ctrlport_req_data,
+ output reg s_ctrlport_resp_ack = 1'b0,
+ output reg [ 1:0] s_ctrlport_resp_status = 2'b00,
+ output reg [31:0] s_ctrlport_resp_data = {32 {1'bX}},
+ // Run state signals that indicate tx and rx operation
+ input wire [3:0] db_state,
+ // GPIO control signals
+ input wire [WIDTH-1:0] gpio_in, //GPIO input state
+ output reg [WIDTH-1:0] gpio_out = {WIDTH {1'b0}}, //GPIO output state
+ output reg [WIDTH-1:0] gpio_ddr = {WIDTH {1'b0}} //GPIO direction (0=input, 1=output)
+);
+
+ `include "../../lib/rfnoc/core/ctrlport.vh"
+ `include "regmap/gpio_atr_regmap_utils.vh"
+
+ reg [WIDTH-1:0] in_atr_state [15:0];
+
+ initial begin
+ in_atr_state[0] = {WIDTH {1'b0}};
+ in_atr_state[1] = {WIDTH {1'b0}};
+ in_atr_state[2] = {WIDTH {1'b0}};
+ in_atr_state[3] = {WIDTH {1'b0}};
+ in_atr_state[4] = {WIDTH {1'b0}};
+ in_atr_state[5] = {WIDTH {1'b0}};
+ in_atr_state[6] = {WIDTH {1'b0}};
+ in_atr_state[7] = {WIDTH {1'b0}};
+ in_atr_state[8] = {WIDTH {1'b0}};
+ in_atr_state[9] = {WIDTH {1'b0}};
+ in_atr_state[10] = {WIDTH {1'b0}};
+ in_atr_state[11] = {WIDTH {1'b0}};
+ in_atr_state[12] = {WIDTH {1'b0}};
+ in_atr_state[13] = {WIDTH {1'b0}};
+ in_atr_state[14] = {WIDTH {1'b0}};
+ in_atr_state[15] = {WIDTH {1'b0}};
+ end
+
+ reg [WIDTH-1:0] ddr_reg, atr_disable, gpio_sw_rb = {WIDTH {1'b0}};
+ reg [WIDTH-1:0] ogpio, igpio = {WIDTH {1'b0}};
+ reg [WIDTH-1:0] classic_atr_select = {WIDTH {1'b0}};
+
+ // DB state/Classic ATR selector
+ reg atr_mode = 1'b0;
+
+ genvar state;
+ //---------------------------------------------------------------------------
+ // Control interface handling
+ //---------------------------------------------------------------------------
+
+ // Check that address is within this module's range.
+ wire address_in_range = (s_ctrlport_req_addr >= REG_BASE) && (s_ctrlport_req_addr < REG_BASE + REG_SIZE);
+
+ // Check that address is targeting an ATR state.
+ wire address_is_atr = (s_ctrlport_req_addr >= REG_BASE + ATR_STATE(0)) && (s_ctrlport_req_addr <= REG_BASE + ATR_STATE(15));
+ // Decode the ATR state being addressed.
+ wire [3:0]atr_address = s_ctrlport_req_addr[5:2];
+
+ always @ (posedge ctrlport_clk) begin
+ if (ctrlport_rst) begin
+ s_ctrlport_resp_ack <= 1'b0;
+ s_ctrlport_resp_data <= {32 {1'bX}};
+ s_ctrlport_resp_status <= 2'b00;
+
+ ddr_reg <= {WIDTH {1'b0}};
+ atr_disable <= {WIDTH {1'b0}};
+ classic_atr_select <= {WIDTH {1'b0}};
+ atr_mode <= 1'b0;
+
+ in_atr_state[0] <= {WIDTH {1'b0}};
+ in_atr_state[1] <= {WIDTH {1'b0}};
+ in_atr_state[2] <= {WIDTH {1'b0}};
+ in_atr_state[3] <= {WIDTH {1'b0}};
+ in_atr_state[4] <= {WIDTH {1'b0}};
+ in_atr_state[5] <= {WIDTH {1'b0}};
+ in_atr_state[6] <= {WIDTH {1'b0}};
+ in_atr_state[7] <= {WIDTH {1'b0}};
+ in_atr_state[8] <= {WIDTH {1'b0}};
+ in_atr_state[9] <= {WIDTH {1'b0}};
+ in_atr_state[10] <= {WIDTH {1'b0}};
+ in_atr_state[11] <= {WIDTH {1'b0}};
+ in_atr_state[12] <= {WIDTH {1'b0}};
+ in_atr_state[13] <= {WIDTH {1'b0}};
+ in_atr_state[14] <= {WIDTH {1'b0}};
+ in_atr_state[15] <= {WIDTH {1'b0}};
+
+ end else begin
+ // Write registers
+ if (s_ctrlport_req_wr) begin
+ // Acknowledge by default
+ s_ctrlport_resp_ack <= 1'b1;
+ s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}};
+ s_ctrlport_resp_status <= CTRL_STS_OKAY;
+
+ // Address ATR state writes
+ if(address_is_atr) begin
+ in_atr_state[atr_address][GPIO_STATE_A_MSB:GPIO_STATE_A] <= s_ctrlport_req_data[GPIO_STATE_A_MSB:GPIO_STATE_A];
+ in_atr_state[atr_address][GPIO_STATE_B_MSB:GPIO_STATE_B] <= s_ctrlport_req_data[GPIO_STATE_B_MSB:GPIO_STATE_B];
+ end else begin
+
+ // Address writes to the rest of the register space
+ case (s_ctrlport_req_addr)
+
+ REG_BASE + ATR_OPTION_REGISTRER: begin
+ atr_mode <= s_ctrlport_req_data[ATR_OPTION];
+ end
+
+ REG_BASE + CLASSIC_ATR_CONFIG: begin
+ classic_atr_select[RF_SELECT_A_MSB:RF_SELECT_A] <= s_ctrlport_req_data[RF_SELECT_A_MSB:RF_SELECT_A];
+ classic_atr_select[RF_SELECT_B_MSB:RF_SELECT_B] <= s_ctrlport_req_data[RF_SELECT_B_MSB:RF_SELECT_B];
+ end
+
+ REG_BASE + GPIO_DIR: begin
+ ddr_reg[GPIO_DIR_A_MSB:GPIO_DIR_A] <= s_ctrlport_req_data[GPIO_DIR_A_MSB:GPIO_DIR_A];
+ ddr_reg[GPIO_DIR_B_MSB:GPIO_DIR_B] <= s_ctrlport_req_data[GPIO_DIR_B_MSB:GPIO_DIR_B];
+ end
+
+ REG_BASE + GPIO_DISABLED: begin
+ atr_disable[GPIO_DISABLED_A_MSB:GPIO_DISABLED_A] <= s_ctrlport_req_data[GPIO_DISABLED_A_MSB:GPIO_DISABLED_A];
+ atr_disable[GPIO_DISABLED_B_MSB:GPIO_DISABLED_B] <= s_ctrlport_req_data[GPIO_DISABLED_B_MSB:GPIO_DISABLED_B];
+ end
+
+ // No register implementation for provided address
+ default: begin
+ // Acknowledge and provide error status if address is in range
+ if (address_in_range) begin
+ s_ctrlport_resp_status <= CTRL_STS_CMDERR;
+
+ // No response if out of range
+ end else begin
+ s_ctrlport_resp_ack <= 1'b0;
+ end
+ end
+ endcase
+ end
+
+ // Read registers
+ end else if (s_ctrlport_req_rd) begin
+ // Acknowledge by default
+ s_ctrlport_resp_ack <= 1'b1;
+ s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}};
+ s_ctrlport_resp_status <= CTRL_STS_OKAY;
+
+ // Address ATR state reads
+ if(address_is_atr) begin
+ s_ctrlport_resp_data[GPIO_STATE_A_MSB:GPIO_STATE_A] <= in_atr_state[atr_address][GPIO_STATE_A_MSB:GPIO_STATE_A];
+ s_ctrlport_resp_data[GPIO_STATE_B_MSB:GPIO_STATE_B] <= in_atr_state[atr_address][GPIO_STATE_B_MSB:GPIO_STATE_B];
+ end else begin
+
+ // Address reads to the rest of the register space
+ case (s_ctrlport_req_addr)
+
+ REG_BASE + ATR_OPTION_REGISTRER: begin
+ s_ctrlport_resp_data[ATR_OPTION] <= atr_mode;
+ end
+
+ REG_BASE + CLASSIC_ATR_CONFIG: begin
+ s_ctrlport_resp_data[RF_SELECT_A_MSB:RF_SELECT_A] <= classic_atr_select[RF_SELECT_A_MSB:RF_SELECT_A];
+ s_ctrlport_resp_data[RF_SELECT_B_MSB:RF_SELECT_B] <= classic_atr_select[RF_SELECT_B_MSB:RF_SELECT_B];
+ end
+
+ REG_BASE + GPIO_DIR: begin
+ s_ctrlport_resp_data[GPIO_DIR_A_MSB:GPIO_DIR_A] <= ddr_reg[GPIO_DIR_A_MSB:GPIO_DIR_A];
+ s_ctrlport_resp_data[GPIO_DIR_B_MSB:GPIO_DIR_B] <= ddr_reg[GPIO_DIR_B_MSB:GPIO_DIR_B];
+ end
+
+ REG_BASE + GPIO_DISABLED: begin
+ s_ctrlport_resp_data[GPIO_DISABLED_A_MSB:GPIO_DISABLED_A] <= atr_disable[GPIO_DISABLED_A_MSB:GPIO_DISABLED_A];
+ s_ctrlport_resp_data[GPIO_DISABLED_B_MSB:GPIO_DISABLED_B] <= atr_disable[GPIO_DISABLED_B_MSB:GPIO_DISABLED_B];
+ end
+
+ REG_BASE + GPIO_IN: begin
+ s_ctrlport_resp_data[GPIO_IN_A_MSB:GPIO_IN_A] <= gpio_sw_rb[GPIO_IN_A_MSB:GPIO_IN_A];
+ s_ctrlport_resp_data[GPIO_IN_B_MSB:GPIO_IN_B] <= gpio_sw_rb[GPIO_IN_B_MSB:GPIO_IN_B];
+ end
+
+ // No register implementation for provided address
+ default: begin
+ // Acknowledge and provide error status if address is in range
+ if (address_in_range) begin
+ s_ctrlport_resp_status <= CTRL_STS_CMDERR;
+
+ // No response if out of range
+ end else begin
+ s_ctrlport_resp_ack <= 1'b0;
+ end
+ end
+ endcase
+ end
+
+ end else begin
+ s_ctrlport_resp_ack <= 1'b0;
+ end
+ end
+ end
+
+ genvar i;
+
+ //Pipeline for easier timing closure
+ reg [ 3:0] db_state_d = 4'b0;
+ reg atr_mode_d = 1'b0;
+ reg [WIDTH-1:0] classic_atr_select_d = {WIDTH {1'b0}};
+ always @(posedge ctrlport_clk) begin
+ db_state_d <= db_state;
+ atr_mode_d <= atr_mode;
+ classic_atr_select_d <= classic_atr_select;
+ end
+
+ generate
+ for (i=0; i
+//
+//
+// Describes the behavior of GPIO lines when controlled by the ATR state.
+//
+//
+//
+// Holds a single bit setting for GPIO lines in both ports for a particular ATR sate
+//
+//
+//
+//
+// Describes GPIO behavior for the different ATR states. When @.ATR_OPTION
+// is set to use the DB states, TX and RX states for RF0 and RF1 are
+// combined to create a single vector. This creates 16 different
+// combinations, each with its own register. When @.ATR_OPTION is set to
+// classic ATR, offsets 0x00-0x03 in this register group will be driven
+// in accordance with the state of RF0, and offsets 0x04-0x07 will be
+// driven in accordance with the state of RF1.
+// CLASSIC ATR MAPPING: Idle[RF0:0x00; RF1:0x04], RX[RF0:0x01; RF1:0x05],
+// TX[RF0:0x02; RF1:0x06], FDX[RF0:0x03; RF1:0x07]
+//
+//
+//
+//
+// Controls whether GPIO lines use the TX and RX state of an RF channel
+// (Classic ATR) or the daughterboard state the selector for the
+// @.GPIO_ATR_STATE.
+//
+//
+//
+// Sets the scheme in which RF states in the radio will control GPIO
+// lines. 0 = DB state is used. RF states are combined and the
+// GPIO state is driven based on all 16 @.GPIO_ATR_STATE registers.
+// 1 = Each RF channel has its separate ATR state(Classic ATR).
+// Use register @.CLASSIC_ATR_CONFIG to indicate the RF channel
+// to which each GPIO line responds to.
+//
+//
+//
+//
+//
+// Controls the RF state mapping of each GPIO line when classic
+// ATR mode is active.
+//
+//
+//
+// Set which RF channel's state to reflect in the pins for
+// HDMI connector A when @.ATR_OPTION is set to classic ATR.
+// Controlled in a per-pin basis.
+// 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03)
+// 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)
+//
+//
+//
+//
+// Set which RF channel's state to reflect in the pins of
+// HDMI connector B when @.ATR_OPTION is set to classic ATR.
+// Controlled in a per-pin basis.
+// 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03)
+// 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)
+//
+//
+//
+//
+//
+// Controls the direction of each GPIO signal when controlled by the radio state.
+// 0 = GPIO pin set to input. 1 = GPIO pin set to output
+//
+//
+//
+//
+// Disable ATR Control. DB state 0 will be reflected regardless of the ATR state.
+//
+//
+//
+//
+// Reflects the logic state of each GPIO input.
+//
+//
+//
+//
+//XmlParse xml_off
+ Make sure the GPIO lines between FPGA and GPIO board are not driven by
+ two drivers. Set the DIO registers in PS_CPLD_BASE_REGMAP appropriately.