fpga: x400: Fix x4xx_qsfp_wrapper testbench

Reorder dependencies so that sc_util_v1_0_vl_rfs.sv gets compiled first when using ModelSim. Original-commit: a9395823ed450aefa1c2d0c894dbcf976264365e
2021-06-22 16:24:54 -05:00
parent 29ac752be0
commit 95dfc4af53
1 changed files with 3 additions and 0 deletions
@@ -79,6 +79,8 @@ $(IP_100G_BD_SRCS) \
 # ModelSim Specific
 #-------------------------------------------------

+# Note: ipshared/*/hdl/sc_util_*_rfs.sv needs to be compiled before the rest of
+# the ipshared files.
 IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/axi_eth_dma_bd/, \
 sim/axi_eth_dma_bd.v \
 ip/*/sim/*.h \
@@ -89,6 +91,7 @@ ip/*/bd_0/sim/*.v \
 ip/*/bd_0/ip/ip_*/sim/*.v \
 ip/*/bd_0/ip/ip_*/sim/*.sv \
 ip/*/bd_0/ip/ip_*/sim/*.vhd \
+ipshared/*/hdl/sc_util_*_rfs.sv \
 ipshared/*/hdl/*.sv \
 ipshared/*/hdl/*.v \
 ipshared/*/simulation/*.v \