From 95dfc4af53076da17612bcce9151db1d1d56bda9 Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Thu, 17 Jun 2021 15:17:31 -0500
Subject: [PATCH] fpga: x400: Fix x4xx_qsfp_wrapper testbench

Reorder dependencies so that sc_util_v1_0_vl_rfs.sv gets compiled
first when using ModelSim.


Original-commit: a9395823ed450aefa1c2d0c894dbcf976264365e
---
 top/x400/sim/x4xx_qsfp_wrapper/Makefile | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/top/x400/sim/x4xx_qsfp_wrapper/Makefile b/top/x400/sim/x4xx_qsfp_wrapper/Makefile
index b38f307..cc0033c 100644
--- a/top/x400/sim/x4xx_qsfp_wrapper/Makefile
+++ b/top/x400/sim/x4xx_qsfp_wrapper/Makefile
@@ -79,6 +79,8 @@ $(IP_100G_BD_SRCS) \
 # ModelSim Specific
 #-------------------------------------------------
 
+# Note: ipshared/*/hdl/sc_util_*_rfs.sv needs to be compiled before the rest of
+# the ipshared files.
 IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/axi_eth_dma_bd/, \
 sim/axi_eth_dma_bd.v \
 ip/*/sim/*.h \
@@ -89,6 +91,7 @@ ip/*/bd_0/sim/*.v \
 ip/*/bd_0/ip/ip_*/sim/*.v \
 ip/*/bd_0/ip/ip_*/sim/*.sv \
 ip/*/bd_0/ip/ip_*/sim/*.vhd \
+ipshared/*/hdl/sc_util_*_rfs.sv \
 ipshared/*/hdl/*.sv \
 ipshared/*/hdl/*.v \
 ipshared/*/simulation/*.v \