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fpga: n3xx: Upgrade to Vivado 2021.1

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Original-commit: c9886751dc361e44345a61e9b8bed310c3d8a9c2
This commit is contained in:
Sam O'Brien
2022-08-25 13:55:30 -05:00
committed by skooNI
parent c41bd8f72b
commit 931bd6491a
20 changed files with 1124 additions and 374 deletions
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top/n3xx/sim/dram_fifo/Makefile
+6 -6
View File
@@ -66,13 +66,13 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
MODELSIM_LIBS += \
secureip \
fifo_generator_v13_2_4 \
axi_register_slice_v2_1_19 \
fifo_generator_v13_2_5 \
axi_register_slice_v2_1_24 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_19 \
axi_crossbar_v2_1_20 \
blk_mem_gen_v8_4_3 \
axi_data_fifo_v2_1_18 \
axi_dwidth_converter_v2_1_24 \
axi_crossbar_v2_1_25 \
blk_mem_gen_v8_4_4 \
axi_data_fifo_v2_1_23 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
top/n3xx/sim/dram_fifo_bist/Makefile
+6 -6
View File
@@ -66,13 +66,13 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
MODELSIM_LIBS += \
secureip \
fifo_generator_v13_2_4 \
axi_register_slice_v2_1_19 \
fifo_generator_v13_2_5 \
axi_register_slice_v2_1_24 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_19 \
axi_crossbar_v2_1_20 \
blk_mem_gen_v8_4_3 \
axi_data_fifo_v2_1_18 \
axi_dwidth_converter_v2_1_24 \
axi_crossbar_v2_1_25 \
blk_mem_gen_v8_4_4 \
axi_data_fifo_v2_1_23 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)