diff --git a/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci b/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
index aaba9d9..2c1372a 100644
--- a/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
+++ b/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
@@ -32,7 +32,7 @@
1
1
1
- 0.000
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AXI4LITE
READ_WRITE
0
@@ -63,7 +63,7 @@
1
1
1
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AXI4LITE
READ_WRITE
0
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1
1
1
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AXI4LITE
READ_WRITE
0
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1
1
1
- 0.000
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AXI4LITE
READ_WRITE
0
@@ -156,7 +156,7 @@
1
1
1
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AXI4LITE
READ_WRITE
0
@@ -187,7 +187,7 @@
1
1
1
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AXI4LITE
READ_WRITE
0
@@ -218,7 +218,7 @@
1
1
1
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AXI4LITE
READ_WRITE
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1
1
1
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AXI4LITE
READ_WRITE
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1
1
1
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AXI4LITE
READ_WRITE
0
@@ -311,7 +311,7 @@
1
1
1
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AXI4LITE
READ_WRITE
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1
1
1
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AXI4LITE
READ_WRITE
0
@@ -373,7 +373,7 @@
1
1
1
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AXI4LITE
READ_WRITE
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1
1
1
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AXI4LITE
READ_WRITE
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1
1
1
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AXI4LITE
READ_WRITE
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1
1
1
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AXI4LITE
READ_WRITE
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1
1
1
- 0.000
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AXI4LITE
READ_WRITE
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100000000
100000000
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0
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100000000
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100000000
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0
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100000000
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100000000
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100000000
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100000000
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100000000
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100000000
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100000000
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100000000
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0
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100000000
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100000000
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100000000
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100000000
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100000000
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0
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100000000
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100000000
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
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0
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0
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0
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0
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0
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0
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0
0
100000000
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0
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100000000
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0
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0
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false
100000000
0
@@ -859,7 +916,7 @@
0
0
undef
- 0.000
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0
0
0
@@ -868,110 +925,131 @@
100000000
+ 0
0
- 0.000
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100000000
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0
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100000000
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0
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100000000
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0
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100000000
+ 0
0
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0
0
0
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
@@ -983,90 +1061,108 @@
100000000
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0
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100000000
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0
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0
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undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
@@ -1076,8 +1172,9 @@
100000000
+ 0
0
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0
0
@@ -1088,7 +1185,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -1101,24 +1198,29 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
0
100000000
+ 0
0
- 0.000
- 156.25
+ 0.0
+
+ 156250000
undef
+ 0.0
100000000
+ 0
0
- 0.000
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+ 0
0
- 0.000
+ 0.0
100000000
0
@@ -1127,7 +1229,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -1140,7 +1242,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -1153,7 +1255,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -1166,7 +1268,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -1418,12 +1520,12 @@
TRUE
TRUE
IP_Flow
- 0
+ 6
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -1773,6 +1875,56 @@
+
+
+
diff --git a/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci b/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci
index 344851b..18d72bd 100644
--- a/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci
+++ b/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci
@@ -13,8 +13,9 @@
10000000
+ 0
0
- 0.000
+ 0.0
32
0
0
@@ -38,7 +39,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -71,7 +72,7 @@
1
2
1
- 0.000
+ 0.0
AXI3
READ_WRITE
0
@@ -122,12 +123,12 @@
TRUE
TRUE
IP_Flow
- 19
+ 24
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -145,6 +146,42 @@
+
+
+
diff --git a/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci b/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci
index 2fa5f4c..cdd8aa5 100644
--- a/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci
+++ b/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci
@@ -13,8 +13,9 @@
10000000
+ 0
0
- 0.000
+ 0.0
32
0
0
@@ -38,7 +39,7 @@
1
2
1
- 0.000
+ 0.0
AXI3
READ_WRITE
0
@@ -71,7 +72,7 @@
1
2
1
- 0.000
+ 0.0
AXI4
READ_WRITE
0
@@ -122,12 +123,12 @@
TRUE
TRUE
IP_Flow
- 19
+ 24
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -142,6 +143,44 @@
+
+
+
diff --git a/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci b/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci
index fc8b9e6..da22085 100644
--- a/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci
+++ b/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci
@@ -13,8 +13,9 @@
10000000
+ 0
0
- 0.000
+ 0.0
32
0
0
@@ -38,7 +39,7 @@
1
2
1
- 0.000
+ 0.0
AXI3
READ_WRITE
0
@@ -71,7 +72,7 @@
1
2
1
- 0.000
+ 0.0
AXI4
READ_WRITE
0
@@ -122,12 +123,12 @@
TRUE
TRUE
IP_Flow
- 19
+ 24
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -144,6 +145,44 @@
+
+
+
diff --git a/top/n3xx/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci b/top/n3xx/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
index 26d7060..15add59 100644
--- a/top/n3xx/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
+++ b/top/n3xx/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
@@ -13,13 +13,15 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -43,7 +45,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -59,7 +61,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -68,12 +70,14 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
1
0
@@ -98,7 +102,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -114,7 +118,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -123,8 +127,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -509,12 +514,12 @@
TRUE
TRUE
IP_Flow
- 4
+ 5
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -577,6 +582,22 @@
+
+
+
diff --git a/top/n3xx/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci b/top/n3xx/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
index 2f6ec0d..a84e91e 100644
--- a/top/n3xx/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
+++ b/top/n3xx/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
@@ -13,13 +13,15 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -43,7 +45,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -59,7 +61,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -68,12 +70,14 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
1
0
@@ -98,7 +102,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -114,7 +118,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -123,8 +127,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -509,12 +514,12 @@
TRUE
TRUE
IP_Flow
- 4
+ 5
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -575,6 +580,22 @@
+
+
+
diff --git a/top/n3xx/ip/axi_eth_dma/axi_eth_dma.xci b/top/n3xx/ip/axi_eth_dma/axi_eth_dma.xci
index ec1df69..4a78139 100644
--- a/top/n3xx/ip/axi_eth_dma/axi_eth_dma.xci
+++ b/top/n3xx/ip/axi_eth_dma/axi_eth_dma.xci
@@ -35,7 +35,7 @@
1
2
1
- 0.000
+ 0.0
AXI4
READ_WRITE
0
@@ -50,7 +50,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -63,7 +63,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -76,10 +76,10 @@
64
100000000
0
- 0
- 0
+ 1
+ 1
0
- 0
+ 1
0
0
1
@@ -90,7 +90,7 @@
1
2
1
- 0.000
+ 0.0
AXI4
READ_ONLY
0
@@ -99,8 +99,9 @@
0
100000000
+ 0
0
- 0.000
+ 0.0
32
0
0
@@ -109,10 +110,10 @@
64
100000000
1
- 0
- 0
+ 1
+ 1
0
- 0
+ 1
0
0
0
@@ -123,7 +124,7 @@
2
1
1
- 0.000
+ 0.0
AXI4
WRITE_ONLY
0
@@ -132,8 +133,9 @@
0
100000000
+ 0
0
- 0.000
+ 0.0
32
0
0
@@ -154,7 +156,7 @@
0
1
1
- 0.000
+ 0.0
AXI4
READ_WRITE
0
@@ -164,8 +166,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -177,7 +180,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -190,7 +193,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -218,7 +221,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -228,8 +231,9 @@
0
100000000
+ 0
0
- 0.000
+ 0.0
125
0
zynq
@@ -299,12 +303,12 @@
TRUE
TRUE
IP_Flow
- 20
+ 25
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -332,10 +336,7 @@
-
-
-
@@ -346,10 +347,7 @@
-
-
-
@@ -405,6 +403,73 @@
+
+
+
diff --git a/top/n3xx/ip/axi_interconnect/axi_interconnect.xci b/top/n3xx/ip/axi_interconnect/axi_interconnect.xci
index 8af91b7..449bd8f 100644
--- a/top/n3xx/ip/axi_interconnect/axi_interconnect.xci
+++ b/top/n3xx/ip/axi_interconnect/axi_interconnect.xci
@@ -13,8 +13,9 @@
10000000
+ 0
0
- 0.000
+ 0.0
32
0
0
@@ -38,7 +39,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -69,7 +70,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -100,7 +101,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -131,7 +132,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -162,7 +163,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -193,7 +194,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -224,7 +225,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -255,7 +256,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -286,7 +287,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -317,7 +318,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -348,7 +349,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -379,7 +380,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -410,7 +411,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -441,7 +442,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -472,7 +473,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -503,7 +504,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -536,7 +537,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -567,7 +568,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -598,7 +599,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -629,7 +630,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -660,7 +661,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -691,7 +692,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -722,7 +723,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -753,7 +754,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -784,7 +785,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -815,7 +816,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -846,7 +847,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -877,7 +878,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -908,7 +909,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -939,7 +940,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -970,7 +971,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -1001,7 +1002,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -2252,12 +2253,12 @@
TRUE
TRUE
IP_Flow
- 20
+ 25
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -2667,6 +2668,119 @@
+
+
+
diff --git a/top/n3xx/ip/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci b/top/n3xx/ip/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci
index 80d8104..61d0e18 100644
--- a/top/n3xx/ip/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci
+++ b/top/n3xx/ip/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci
@@ -13,8 +13,9 @@
4096
100000000
+ 0
0
- 0.000
+ 0.0
100000000
1
@@ -23,7 +24,7 @@
0
0
undef
- 0.000
+ 0.0
4
0
0
@@ -36,7 +37,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -49,7 +50,7 @@
0
0
undef
- 0.000
+ 0.0
4
0
0
@@ -82,7 +83,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -113,7 +114,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -135,6 +136,7 @@
0
0
0x80000FFF
+ 0
32768
5
4091
@@ -142,6 +144,7 @@
32
32
4
+ 0
2048
5
2043
@@ -169,6 +172,7 @@
false
false
0x80000FFF
+ 0
32768
5
4091
@@ -178,6 +182,7 @@
32
4
AXI4LITE
+ 0
2048
5
2043
@@ -201,12 +206,12 @@
TRUE
TRUE
IP_Flow
- 1
+ 6
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -260,6 +265,34 @@
+
+
+
diff --git a/top/n3xx/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/top/n3xx/ip/fifo_4k_2clk/fifo_4k_2clk.xci
index 8888402..5c52fdf 100644
--- a/top/n3xx/ip/fifo_4k_2clk/fifo_4k_2clk.xci
+++ b/top/n3xx/ip/fifo_4k_2clk/fifo_4k_2clk.xci
@@ -13,13 +13,15 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -43,7 +45,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -59,7 +61,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -68,12 +70,14 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
1
0
@@ -98,7 +102,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -114,7 +118,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -123,8 +127,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -509,12 +514,12 @@
TRUE
TRUE
IP_Flow
- 4
+ 5
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -569,6 +574,14 @@
+
+
+
diff --git a/top/n3xx/ip/fifo_short_2clk/fifo_short_2clk.xci b/top/n3xx/ip/fifo_short_2clk/fifo_short_2clk.xci
index cc0f896..249357e 100644
--- a/top/n3xx/ip/fifo_short_2clk/fifo_short_2clk.xci
+++ b/top/n3xx/ip/fifo_short_2clk/fifo_short_2clk.xci
@@ -13,13 +13,15 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -43,7 +45,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -59,7 +61,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -68,12 +70,14 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
1
0
@@ -98,7 +102,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -114,7 +118,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -123,8 +127,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -509,12 +514,12 @@
TRUE
TRUE
IP_Flow
- 4
+ 5
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -571,6 +576,14 @@
+
+
+
diff --git a/top/n3xx/ip/hb47_1to2/hb47_1to2.xci b/top/n3xx/ip/hb47_1to2/hb47_1to2.xci
index a192027..8d1b642 100644
--- a/top/n3xx/ip/hb47_1to2/hb47_1to2.xci
+++ b/top/n3xx/ip/hb47_1to2/hb47_1to2.xci
@@ -9,11 +9,11 @@
hb47_1to2
- ACTIVE_LOW
100000000
+ 0
0
- 0.000
+ 0.0
0
1
1
@@ -30,7 +30,7 @@
0
0
undef
- 0.000
+ 0.0
12
0
0
@@ -43,7 +43,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -56,7 +56,7 @@
0
0
undef
- 0.000
+ 0.0
4
0
0
@@ -69,7 +69,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -151,6 +151,7 @@
Vector
-62, 0, 194, 0, -440, 0, 855, 0, -1505, 0, 2478, 0, -3900, 0, 5990, 0, -9187, 0, 14632, 0, -26536, 0, 83009, 131071, 83009, 0, -26536, 0, 14632, 0, -9187, 0, 5990, 0, -3900, 0, 2478, 0, -1505, 0, 855, 0, -440, 0, 194, 0, -62
Automatic
+ false
no_coe_file_loaded
0
false
@@ -160,13 +161,20 @@
18
24
hb47_1to2
+ false
+ false
+ false
+ false
Not_Required
1
Automatic
0
+ false
+ false
Signed
16
1
+ false
false
Systolic_Multiply_Accumulate
1
@@ -184,18 +192,23 @@
true
Not_Required
Automatic
+ false
+ false
1
1
2
+ false
Area
None
None
+ false
Automatic
Non_Symmetric_Rounding_Up
18
0.5
0.0
P4-0,P4-1,P4-2,P4-3,P4-4
+ false
Automatic
Integer_Coefficients
Output_Sample_Period
@@ -226,12 +239,12 @@
TRUE
TRUE
IP_Flow
- 12
+ 16
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -287,6 +300,24 @@
+
+
+
diff --git a/top/n3xx/ip/hb47_2to1/hb47_2to1.xci b/top/n3xx/ip/hb47_2to1/hb47_2to1.xci
index 7a8522f..d737b6f 100644
--- a/top/n3xx/ip/hb47_2to1/hb47_2to1.xci
+++ b/top/n3xx/ip/hb47_2to1/hb47_2to1.xci
@@ -9,11 +9,11 @@
hb47_2to1
- ACTIVE_LOW
100000000
+ 0
0
- 0.000
+ 0.0
0
1
1
@@ -30,7 +30,7 @@
0
0
undef
- 0.000
+ 0.0
6
0
0
@@ -43,7 +43,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -56,7 +56,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -69,7 +69,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -78,7 +78,7 @@
35,35,35,35
fixed
hb47_2to1.mif
- 47
+ 24
2
0
0,0,0,0
@@ -86,7 +86,7 @@
18,18,18,18
0
18
- 47
+ 24
1
4
hb47_2to1
@@ -115,15 +115,15 @@
1
1
2
- 52
- 2
+ 30
+ 1
0
0
48
1
1
1
- 47
+ 24
1
47
0
@@ -137,7 +137,7 @@
2,3,2,3
1
7
- 0
+ 1
0
0
64
@@ -151,6 +151,7 @@
COE_File
6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
Automatic
+ false
hb47.coe
0
false
@@ -158,15 +159,22 @@
Signed
Inferred
18
- 47
+ 24
hb47_2to1
+ false
+ false
+ false
+ false
Not_Required
1
Automatic
0
+ false
+ false
Signed
16
2
+ false
false
Systolic_Multiply_Accumulate
1
@@ -184,18 +192,23 @@
false
Not_Required
Automatic
+ false
+ false
1
1
2
+ false
Area
None
None
+ false
Automatic
Non_Symmetric_Rounding_Up
17
0.4
0.0
P4-0,P4-1,P4-2,P4-3,P4-4
+ false
Automatic
Integer_Coefficients
Input_Sample_Period
@@ -226,12 +239,12 @@
TRUE
TRUE
IP_Flow
- 12
+ 16
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -303,6 +316,24 @@
+
+
+
diff --git a/top/n3xx/ip/misc_clock_gen/misc_clock_gen.xci b/top/n3xx/ip/misc_clock_gen/misc_clock_gen.xci
index 2a2cc31..6f6296b 100644
--- a/top/n3xx/ip/misc_clock_gen/misc_clock_gen.xci
+++ b/top/n3xx/ip/misc_clock_gen/misc_clock_gen.xci
@@ -21,34 +21,39 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
LEVEL_HIGH
100000000
+ 0
0
- 0.000
+ 0.0
0
0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -72,7 +77,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -98,14 +103,14 @@
100.0
0000
0000
- 198.413
+ 198.41270
0000
0000
- 303.819
+ 303.81945
BUFGCE
50.0
false
- 198.413
+ 198.41270
0.000
50.0
198.412704761
@@ -117,7 +122,7 @@
BUFGCE
50.0
false
- 303.819
+ 303.81945
0.000
50.0
305.55555
@@ -203,15 +208,17 @@
din
0000
1
- 0.6493506819332852
- 1.98412704761
- 1.98412704761
- 1.98412704761
- 1.98412704761
- 1.98412704761
+ 0.6530612244897959
+ 0.16326530612244897
+ 0.16326530612244897
+ 0.16326530612244897
+ 0.16326530612244897
+ 0.16326530612244897
dout
drdy
dwe
+ 93.000
+ 1.000
0
0
0
@@ -285,11 +292,14 @@
0.010
0.010
FALSE
+ 64.000
+ 2.000
2
+ 0
Output Output Phase Duty Cycle Pk-to-Pk Phase
Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
- meas_clk___198.413______0.000______50.0______113.755____141.292
- ddr3_dma_clk___303.819______0.000______50.0______105.705____141.292
+ meas_clk__198.41270______0.000______50.0______113.755____141.292
+ ddr3_dma_clk__303.81945______0.000______50.0______105.705____141.292
no_CLK_OUT3_output
no_CLK_OUT4_output
no_CLK_OUT5_output
@@ -297,6 +307,8 @@
no_CLK_OUT7_output
0
0
+ 128.000
+ 1.000
WAVEFORM
UNKNOWN
false
@@ -387,6 +399,8 @@
1
0
0
+ 1440.000
+ 600.000
misc_clock_gen
MMCM
false
@@ -559,6 +573,7 @@
0.010
false
2
+ false
false
false
WAVEFORM
@@ -657,12 +672,12 @@
TRUE
TRUE
IP_Flow
- 3
+ 8
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -732,6 +747,15 @@
+
+
+
diff --git a/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl b/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl
index 206a05a..f355663 100644
--- a/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl
+++ b/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
-set scripts_vivado_version 2019.1
+set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
- catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
@@ -76,10 +76,10 @@ if { ${design_name} eq "" } {
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
- common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty."
+ common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
- common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+ common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
@@ -100,19 +100,19 @@ if { ${design_name} eq "" } {
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
- common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+ common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
- common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+ common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
-common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"."
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"."
if { $nRet != 0 } {
- catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
@@ -123,7 +123,7 @@ set bCheckIPsPassed 1
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
-xilinx.com:ip:axi_iic:2.0\
+xilinx.com:ip:axi_iic:2.1\
xilinx.com:ip:axi_uartlite:2.0\
ettus.com:ip:axi_bitq:1.0\
xilinx.com:ip:processing_system7:5.5\
@@ -134,7 +134,7 @@ xilinx.com:ip:axi_protocol_converter:2.1\
"
set list_ips_missing ""
- common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
@@ -144,14 +144,14 @@ xilinx.com:ip:axi_protocol_converter:2.1\
}
if { $list_ips_missing ne "" } {
- catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
- common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
@@ -166,21 +166,21 @@ proc create_hier_cell_dma { parentCell nameHier } {
variable script_folder
if { $parentCell eq "" || $nameHier eq "" } {
- catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_dma() - Empty argument(s)!"}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_dma() - Empty argument(s)!"}
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
- catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
- catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."}
return
}
@@ -288,14 +288,14 @@ proc create_root_design { parentCell } {
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
- catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
- catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."}
return
}
@@ -650,11 +650,10 @@ proc create_root_design { parentCell } {
set JTAG1_TDO [ create_bd_port -dir I JTAG1_TDO ]
set JTAG1_TMS [ create_bd_port -dir IO JTAG1_TMS ]
set MIO [ create_bd_port -dir IO -from 53 -to 0 MIO ]
- set M_AXI_WR_CLK [ create_bd_port -dir I -type clk M_AXI_WR_CLK ]
+ set M_AXI_WR_CLK [ create_bd_port -dir I -type clk -freq_hz 62500000 M_AXI_WR_CLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {M_AXI_WR} \
CONFIG.ASSOCIATED_RESET {M_AXI_WR_RSTn} \
- CONFIG.FREQ_HZ {62500000} \
] $M_AXI_WR_CLK
set M_AXI_WR_RSTn [ create_bd_port -dir I -type rst M_AXI_WR_RSTn ]
set PS_CLK [ create_bd_port -dir IO PS_CLK ]
@@ -688,41 +687,33 @@ proc create_root_design { parentCell } {
set SPI1_SS_I [ create_bd_port -dir I SPI1_SS_I ]
set SPI1_SS_O [ create_bd_port -dir O SPI1_SS_O ]
set SPI1_SS_T [ create_bd_port -dir O SPI1_SS_T ]
- set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk S_AXI_GP0_ACLK ]
+ set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk -freq_hz 40000000 S_AXI_GP0_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_RESET {S_AXI_GP0_ARESETN} \
- CONFIG.FREQ_HZ {40000000} \
] $S_AXI_GP0_ACLK
set S_AXI_GP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP0_ARESETN ]
- set S_AXI_GP1_ACLK [ create_bd_port -dir I -type clk S_AXI_GP1_ACLK ]
+ set S_AXI_GP1_ACLK [ create_bd_port -dir I -type clk -freq_hz 40000000 S_AXI_GP1_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_RESET {S_AXI_GP1_ARESETN} \
- CONFIG.FREQ_HZ {40000000} \
] $S_AXI_GP1_ACLK
set S_AXI_GP1_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP1_ARESETN ]
- set S_AXI_HP0_ACLK [ create_bd_port -dir I -type clk S_AXI_HP0_ACLK ]
- set_property -dict [ list \
- CONFIG.FREQ_HZ {40000000} \
- ] $S_AXI_HP0_ACLK
+ set S_AXI_HP0_ACLK [ create_bd_port -dir I -type clk -freq_hz 40000000 S_AXI_HP0_ACLK ]
set S_AXI_HP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_HP0_ARESETN ]
- set S_AXI_HP1_ACLK [ create_bd_port -dir I -type clk S_AXI_HP1_ACLK ]
+ set S_AXI_HP1_ACLK [ create_bd_port -dir I -type clk -freq_hz 40000000 S_AXI_HP1_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_RESET {S_AXI_HP1_ARESETN} \
- CONFIG.FREQ_HZ {40000000} \
] $S_AXI_HP1_ACLK
set S_AXI_HP1_ARESETN [ create_bd_port -dir I -type rst S_AXI_HP1_ARESETN ]
- set bus_clk [ create_bd_port -dir I -type clk bus_clk ]
+ set bus_clk [ create_bd_port -dir I -type clk -freq_hz 200000000 bus_clk ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {m_axis_dma:s_axis_dma} \
CONFIG.ASSOCIATED_RESET {bus_rstn} \
- CONFIG.FREQ_HZ {200000000} \
] $bus_clk
set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ]
- set clk40 [ create_bd_port -dir I -type clk clk40 ]
+ set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ]
set_property -dict [ list \
- CONFIG.ASSOCIATED_BUSIF {M_AXI_NET0:M_AXI_NET1:M_AXI_XBAR:M_AXI_JESD0:M_AXI_JESD1:M_AXI_ETH_DMA0:M_AXI_ETH_DMA1:M_AXI_NET2} \
+ CONFIG.ASSOCIATED_BUSIF {M_AXI_NET0:M_AXI_NET1:M_AXI_XBAR:M_AXI_JESD0:M_AXI_JESD1:M_AXI_ETH_DMA0:M_AXI_ETH_DMA1:M_AXI_NET2:m_axi_eth_internal} \
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
- CONFIG.FREQ_HZ {40000000} \
] $clk40
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
set qsfp_scl_i [ create_bd_port -dir I qsfp_scl_i ]
@@ -733,7 +724,7 @@ proc create_root_design { parentCell } {
set qsfp_sda_t [ create_bd_port -dir O qsfp_sda_t ]
# Create instance: axi_iic_0, and set properties
- set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ]
+ set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.1 axi_iic_0 ]
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
@@ -762,6 +753,7 @@ proc create_root_design { parentCell } {
set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
set_property -dict [ list \
CONFIG.C_BAUDRATE {115200} \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {40000000} \
] $axi_uartlite_0
# Create instance: dma
@@ -1102,8 +1094,12 @@ proc create_root_design { parentCell } {
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_9_PULLUP {enabled} \
CONFIG.PCW_MIO_9_SLEW {slow} \
- CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#I2C Reset#GPIO#GPIO#ENET Reset#USB Reset#UART 1#UART 1#PJTAG#PJTAG#PJTAG#PJTAG#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#GPIO#GPIO#GPIO#I2C 0#I2C 0#GPIO#GPIO} \
- CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#reset#gpio[4]#gpio[5]#reset#reset#tx#rx#tdi#tdo#tck#tms#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#gpio[47]#gpio[48]#gpio[49]#scl#sda#gpio[52]#gpio[53]} \
+ CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#I2C Reset#GPIO#GPIO#ENET Reset#USB Reset#UART 1#UART\
+1#PJTAG#PJTAG#PJTAG#PJTAG#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet\
+0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB\
+0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD\
+0#GPIO#GPIO#GPIO#GPIO#I2C 0#I2C 0#GPIO#GPIO}\
+ CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#reset#gpio[4]#gpio[5]#reset#reset#tx#rx#tdi#tdo#tck#tms#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#gpio[47]#gpio[48]#gpio[49]#scl#sda#gpio[52]#gpio[53]}\
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_PJTAG_PJTAG_IO {MIO 10 .. 13} \
@@ -1313,28 +1309,28 @@ proc create_root_design { parentCell } {
connect_bd_net -net xlslice_2_Dout [get_bd_pins xlconcat_0/In0] [get_bd_pins xlslice_2/Dout]
# Create address segments
- create_bd_addr_seg -range 0x00004000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_ETH_DMA0/Reg] SEG_M_AXI_ETH_DMA0_Reg
- create_bd_addr_seg -range 0x00004000 -offset 0x40008000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_ETH_DMA1/Reg] SEG_M_AXI_ETH_DMA1_Reg
- create_bd_addr_seg -range 0x00004000 -offset 0x40014000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_JESD0/Reg] SEG_M_AXI_JESD0_Reg
- create_bd_addr_seg -range 0x00004000 -offset 0x40018000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_JESD1/Reg] SEG_M_AXI_JESD1_Reg
- create_bd_addr_seg -range 0x00004000 -offset 0x40004000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET0/Reg] SEG_M_AXI_NET0_Reg
- create_bd_addr_seg -range 0x00004000 -offset 0x4000C000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET1/Reg] SEG_M_AXI_NET1_Reg
- create_bd_addr_seg -range 0x00020000 -offset 0x40020000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET2/Reg] SEG_M_AXI_NET2_Reg
- create_bd_addr_seg -range 0x00040000 -offset 0x43D40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_WR/Reg] SEG_M_AXI_WR_Reg
- create_bd_addr_seg -range 0x00004000 -offset 0x40010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_XBAR/Reg] SEG_M_AXI_XBAR_Reg
- create_bd_addr_seg -range 0x00001000 -offset 0x42C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_WR_UART_Reg
- create_bd_addr_seg -range 0x00004000 -offset 0x40040000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_dma_eth_internal/S_AXI_LITE/Reg] SEG_axi_dma_eth_internal_Reg
- create_bd_addr_seg -range 0x00010000 -offset 0x43D80000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg
- create_bd_addr_seg -range 0x00001000 -offset 0x42100000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs jtag_0/S_AXI/reg0] SEG_jtag_0_reg0
- create_bd_addr_seg -range 0x00001000 -offset 0x42200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs jtag_1/S_AXI/reg0] SEG_jtag_1_reg0
- create_bd_addr_seg -range 0x00004000 -offset 0x40050000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_eth_internal/Reg] SEG_m_axi_eth_internal_Reg
- create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM
- create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
- create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM
- create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces S_AXI_GP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_GP0_DDR_LOWOCM
- create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces S_AXI_GP1] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_GP1_DDR_LOWOCM
- create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces S_AXI_HP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM
- create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces S_AXI_HP1] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
+ assign_bd_address -offset 0x40000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_ETH_DMA0/Reg] -force
+ assign_bd_address -offset 0x40008000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_ETH_DMA1/Reg] -force
+ assign_bd_address -offset 0x40014000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_JESD0/Reg] -force
+ assign_bd_address -offset 0x40018000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_JESD1/Reg] -force
+ assign_bd_address -offset 0x40004000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET0/Reg] -force
+ assign_bd_address -offset 0x4000C000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET1/Reg] -force
+ assign_bd_address -offset 0x40020000 -range 0x00020000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET2/Reg] -force
+ assign_bd_address -offset 0x43D40000 -range 0x00040000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_WR/Reg] -force
+ assign_bd_address -offset 0x40010000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_XBAR/Reg] -force
+ assign_bd_address -offset 0x40040000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_dma_eth_internal/S_AXI_LITE/Reg] -force
+ assign_bd_address -offset 0x43D80000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_iic_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x42C00000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x42100000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs jtag_0/S_AXI/reg0] -force
+ assign_bd_address -offset 0x42200000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs jtag_1/S_AXI/reg0] -force
+ assign_bd_address -offset 0x40050000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_eth_internal/Reg] -force
+ assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
+ assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] -force
+ assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] -force
+ assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S_AXI_GP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
+ assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S_AXI_HP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
+ assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S_AXI_GP1] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] -force
+ assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S_AXI_HP1] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] -force
# Restore current instance
@@ -1352,3 +1348,4 @@ proc create_root_design { parentCell } {
create_root_design ""
+
diff --git a/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci b/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci
index 79d8850..cfc8874 100644
--- a/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci
+++ b/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci
@@ -7,7 +7,7 @@
one_gig_eth_pcs_pma
-
+
1
1
@@ -16,51 +16,63 @@
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
false
false
false
@@ -69,37 +81,54 @@
+ 0
0
+ 0
0
false
100000000
+ 0
0
+ 0
0
100000000
+ 0
0
- 0.000
+ 0.0
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
100000000
0
- 0.000
+ 0.0
100000000
0
- 0.000
+ 0.0
false
false
false
@@ -110,14 +139,16 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
false
false
false
@@ -125,29 +156,35 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
ACTIVE_LOW
ACTIVE_LOW
@@ -176,7 +213,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -187,31 +224,38 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
true
0
+ 0
0
false
false
@@ -221,7 +265,7 @@
DIFF_PAIR_0
DIFF_PAIR_1
zynq
- 0
+ Sync
one_gig_eth_pcs_pma
50
false
@@ -314,12 +358,12 @@
TRUE
TRUE
IP_Flow
- 6
+ 4
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -346,6 +390,31 @@
+
+
+
diff --git a/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci b/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
index 8af7da8..85a8ba8 100644
--- a/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
+++ b/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
@@ -16,18 +16,21 @@
0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -37,14 +40,16 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
false
0
@@ -53,83 +58,98 @@
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
false
0
0
+ 0
0
- 0.000
+ 0.0
0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
0
ten_gig_eth_pcs_pma
100.00
@@ -179,14 +199,45 @@
TRUE
TRUE
IP_Flow
- 15
+ 19
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
+
+
+
+
+
+
+
diff --git a/top/n3xx/setupenv.sh b/top/n3xx/setupenv.sh
index d3057d5..ef985b1 100644
--- a/top/n3xx/setupenv.sh
+++ b/top/n3xx/setupenv.sh
@@ -1,6 +1,6 @@
#!/bin/bash
-VIVADO_VER=2019.1
+VIVADO_VER=2021.1
DISPLAY_NAME="USRP-N3x0"
REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)
diff --git a/top/n3xx/sim/dram_fifo/Makefile b/top/n3xx/sim/dram_fifo/Makefile
index 1ca7ef7..0669aaa 100644
--- a/top/n3xx/sim/dram_fifo/Makefile
+++ b/top/n3xx/sim/dram_fifo/Makefile
@@ -66,13 +66,13 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
MODELSIM_LIBS += \
secureip \
-fifo_generator_v13_2_4 \
-axi_register_slice_v2_1_19 \
+fifo_generator_v13_2_5 \
+axi_register_slice_v2_1_24 \
axi_infrastructure_v1_1_0 \
-axi_dwidth_converter_v2_1_19 \
-axi_crossbar_v2_1_20 \
-blk_mem_gen_v8_4_3 \
-axi_data_fifo_v2_1_18 \
+axi_dwidth_converter_v2_1_24 \
+axi_crossbar_v2_1_25 \
+blk_mem_gen_v8_4_4 \
+axi_data_fifo_v2_1_23 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
diff --git a/top/n3xx/sim/dram_fifo_bist/Makefile b/top/n3xx/sim/dram_fifo_bist/Makefile
index 122dfff..b2959a2 100644
--- a/top/n3xx/sim/dram_fifo_bist/Makefile
+++ b/top/n3xx/sim/dram_fifo_bist/Makefile
@@ -66,13 +66,13 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
MODELSIM_LIBS += \
secureip \
-fifo_generator_v13_2_4 \
-axi_register_slice_v2_1_19 \
+fifo_generator_v13_2_5 \
+axi_register_slice_v2_1_24 \
axi_infrastructure_v1_1_0 \
-axi_dwidth_converter_v2_1_19 \
-axi_crossbar_v2_1_20 \
-blk_mem_gen_v8_4_3 \
-axi_data_fifo_v2_1_18 \
+axi_dwidth_converter_v2_1_24 \
+axi_crossbar_v2_1_25 \
+blk_mem_gen_v8_4_4 \
+axi_data_fifo_v2_1_23 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)