x300 fpga: updating FPGA code with latest bug fixes

Original-commit: 847b7a631f5e73d732c88a4b4aa91595cf4e4a07

top/x300/bus_int.v

@@ -43,8 +43,8 @@ module bus_int
     inout SFPP1_RS0,
     inout SFPP1_RS1,
     //
-    input [3:0] clock_status,
+    input [4:0] clock_status,
-    output [5:0] clock_control,
+    output [6:0] clock_control,
     // ETH0
     output [63:0] eth0_tx_tdata, output [3:0] eth0_tx_tuser, output eth0_tx_tlast, output eth0_tx_tvalid, input eth0_tx_tready,
     input [63:0] eth0_rx_tdata, input [3:0] eth0_rx_tuser, input eth0_rx_tlast, input eth0_rx_tvalid, output eth0_rx_tready,
@@ -141,7 +141,7 @@ module bus_int
    localparam RB_BIST         = 8'd128;
 
 
-   localparam COMPAT_MAJOR    = 16'h0003;
+   localparam COMPAT_MAJOR    = 16'h0004;
    localparam COMPAT_MINOR    = 16'h0000;
 
    wire [31:0] 	  set_data;
@@ -295,8 +295,8 @@ module bus_int
       .strobe(set_stb), .addr(set_addr), .in(set_data),
       .out(sw_rst));
 
-   setting_reg #(.my_addr(SR_CLOCK_CTRL), .awidth(SR_AWIDTH), .width(6),
+   setting_reg #(.my_addr(SR_CLOCK_CTRL), .awidth(SR_AWIDTH), .width(7),
-        .at_reset(6'b100000) //bit 5 high means GPSDO on by default
+        .at_reset(7'b1000000) //bit 6 high means GPSDO on by default
     ) set_clk_ctrl
      (.clk(clk), .rst(reset),
       .strobe(set_stb), .addr(set_addr), .in(set_data),
@@ -341,7 +341,7 @@ module bus_int
        RB_COUNTER: rb_data = counter;
        RB_SPI_RDY: rb_data = {31'b0, spi_ready};
        RB_SPI_DATA: rb_data = rb_spi_data;
-       RB_CLK_STATUS: rb_data = {28'b0, clock_status};
+       RB_CLK_STATUS: rb_data = {27'b0, clock_status};
        // SFPP Interface pins.
        RB_SFPP_STATUS0: rb_data = {26'b0,SFPP0_ModAbs_chgd,SFPP0_TxFault_chgd,SFPP0_RxLOS_chgd,
 				  SFPP0_ModAbs_reg2,SFPP0_TxFault_reg2,SFPP0_RxLOS_reg2};

top/x300/capture_ddrlvds.v

@@ -7,7 +7,7 @@
 
 module capture_ddrlvds
   #(parameter WIDTH=7,
-    parameter B250=0)
+    parameter X300=0)
    (input clk,
     input reset,
     input ssclk_p,
@@ -52,7 +52,7 @@ module capture_ddrlvds
    generate
       for(i = 0; i < WIDTH; i = i + 1)
 	begin : gen_lvds_pins
-	   if ((i == 10) && (B250 == 1)) begin
+	   if ((i == 10) && (X300 == 1)) begin
 	      IBUFDS #(.DIFF_TERM("FALSE")) ibufds
 		(.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) );
 	      IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) iddr

top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v

@@ -259,7 +259,7 @@ module ten_gig_eth_pcs_pma_x300_top
 
  // assign core_clk156_out = clk156;
 
-   // Not needed in B250
+   // Not needed in X300
 /* -----\/----- EXCLUDED -----\/-----
 
   ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) rx_clk_ddr(

top/x300/x300.v

@@ -381,8 +381,40 @@ module x300
       );
 
    ////////////////////////////////////////////////////////////////////
+   // PPS
+   // Support for internal, external, and GPSDO PPS inputs
+   // Every attempt to minimize propagation between the external PPS
+   // input and outputs to support daisy-chaining the signal.
+   ////////////////////////////////////////////////////////////////////
+
+   // Generate an internal PPS signal with a 25% duty cycle
+   reg [31:0] pps_count;
+   wire int_pps = (pps_count < 32'd2500000);
+   always @(posedge ref_clk_10mhz) begin
+      if (pps_count >= 32'd9999999)
+         pps_count <= 32'b0;
+      else
+         pps_count <= pps_count + 1'b1;
+   end
+
+   // PPS MUX - selects internal, external, or gpsdo PPS
+   reg pps;
+   wire [1:0] pps_select;
+   wire pps_out_enb;
+   always @(*) begin
+      case(pps_select)
+         2'b00  :   pps = EXT_PPS_IN;
+         2'b01  :   pps = 1'b0;
+         2'b10  :   pps = int_pps;
+         2'b11  :   pps = GPS_PPS_OUT;
+         default:   pps = 1'b0;
+      endcase
+   end
+
+   // PPS out and LED
+   assign EXT_PPS_OUT = pps & pps_out_enb;
+   assign LED_PPS = ~pps;                                  // active low LED driver
 
-   assign LED_PPS = ~(GPS_PPS_OUT | EXT_PPS_IN);
    assign LED_GPSLOCK = ~GPS_LOCK_OK;
    assign LED_REFLOCK = ~LMK_Lock;
    assign {LED_RX1_RX,LED_TXRX1_TX,LED_TXRX1_RX} = ~led0;  // active low LED driver
@@ -451,7 +483,7 @@ module x300
    // Analog diff pairs on I side of ADC are inverted for layout reasons, but data diff pairs are all swapped as well
    //  so I gets a double negative, and is unchanged.  Q must be inverted.
 
-   capture_ddrlvds #(.WIDTH(14),.B250(1)) cap_db0
+   capture_ddrlvds #(.WIDTH(14),.X300(1)) cap_db0
      (.clk(radio_clk), .reset(radio_rst), .ssclk_p(DB0_ADC_DCLK_P), .ssclk_n(DB0_ADC_DCLK_N),
       .in_p({{DB0_ADC_DA6_P, DB0_ADC_DA5_P, DB0_ADC_DA4_P, DB0_ADC_DA3_P, DB0_ADC_DA2_P, DB0_ADC_DA1_P, DB0_ADC_DA0_P},
          {DB0_ADC_DB6_P, DB0_ADC_DB5_P, DB0_ADC_DB4_P, DB0_ADC_DB3_P, DB0_ADC_DB2_P, DB0_ADC_DB1_P, DB0_ADC_DB0_P}}),
@@ -461,7 +493,7 @@ module x300
       .out({rx0_i,rx0_q_inv}));
    assign rx0[31:0] = { rx0_i, 2'b00, ~rx0_q_inv, 2'b00 };
 
-   capture_ddrlvds #(.WIDTH(14),.B250(1)) cap_db1
+   capture_ddrlvds #(.WIDTH(14),.X300(1)) cap_db1
      (.clk(radio_clk),  .reset(radio_rst), .ssclk_p(DB1_ADC_DCLK_P), .ssclk_n(DB1_ADC_DCLK_N),
       .in_p({{DB1_ADC_DA6_P, DB1_ADC_DA5_P, DB1_ADC_DA4_P, DB1_ADC_DA3_P, DB1_ADC_DA2_P, DB1_ADC_DA1_P, DB1_ADC_DA0_P},
          {DB1_ADC_DB6_P, DB1_ADC_DB5_P, DB1_ADC_DB4_P, DB1_ADC_DB3_P, DB1_ADC_DB2_P, DB1_ADC_DB1_P, DB1_ADC_DB0_P}}),
@@ -1756,7 +1788,7 @@ module x300
 
    ///////////////////////////////////////////////////////////////////////////////////
    //
-   // B250 Core
+   // X300 Core
    //
    ///////////////////////////////////////////////////////////////////////////////////
    x300_core x300_core
@@ -1836,10 +1868,10 @@ module x300
       .gmii_txd1(gmii_txd1), .gmii_tx_en1(gmii_tx_en1), .gmii_tx_er1(gmii_tx_er1),
       .gmii_rxd1(gmii_rxd1), .gmii_rx_dv1(gmii_rx_dv1), .gmii_rx_er1(gmii_rx_er1),
 `endif // !`ifdef
+      // Time
+      .pps(pps),.pps_select(pps_select), .pps_out_enb(pps_out_enb),
       // GPS Signals
-      .gps_pps(GPS_PPS_OUT), .ext_pps(EXT_PPS_IN),
       .gps_txd(GPS_SER_IN), .gps_rxd(GPS_SER_OUT),
-      .pps_out(EXT_PPS_OUT),
       // Debug UART
       .debug_rxd(debug_rxd), .debug_txd(debug_txd),
       // Misc.

top/x300/x300_core.v

@@ -104,9 +104,9 @@ module x300_core
 `endif // !`ifdef
 
    // Time
-   input gps_pps,
+   input pps,
-   input ext_pps,
+   output [1:0] pps_select,
-   output reg pps_out,
+   output pps_out_enb,
    output gps_txd,
    input gps_rxd,
    // Debug UART
@@ -369,31 +369,20 @@ module x300_core
 
 
     /////////////////////////////////////////////////////////////////////////////////
-    // PPS synchronization and generation logic
+    // PPS synchronization logic
     /////////////////////////////////////////////////////////////////////////////////
-
     //PPS input signals will be flopped in via the 10MHz reference clock.
     //Its assumed that the radio clock, which is derived from the 10MHz,
     //will be able to flop this captured PPS signal without metastability.
     //And that the relation of the radio clock to this ref clock will be
     //consistent enough across multiple units to use for this purpose.
-    reg [1:0] 	 ext_pps_del, gps_pps_del;
+    reg [1:0] pps_del;
-    always @(posedge ext_ref_clk) ext_pps_del[1:0] <= {ext_pps_del[0], ext_pps};
+    always @(posedge ext_ref_clk)  pps_del[1:0] <= {pps_del[0], pps};
-    always @(posedge ext_ref_clk) gps_pps_del[1:0] <= {gps_pps_del[0], gps_pps};
 
-    //Generate a PPS signal disciplined by the input reference PPS.
+    //PPS detection - toggle pps_detect on each PPS rising edge.
-    //The PPS signal is 25% duty cycle, and generated by the rising edge.
+    reg pps_detect;
-    reg pps_int;
-    wire pps_out_enb, pps_select;
-    reg [31:0] pps_count;
-    wire pps_duty_high = (pps_count < 32'd2500000);
-    wire pps_edge = pps_select? (ext_pps_del == 2'b01) : (gps_pps_del == 2'b01);
     always @(posedge ext_ref_clk) begin
-        if (pps_edge) pps_count <= 32'd3; //delay = sampling + detection + flopping out
+        if (pps_del == 2'b01) pps_detect <= ~pps_detect;
-        else if (pps_count == 32'd9999999) pps_count <= 32'b0;
-        else pps_count <= pps_count + 1'b1;
-        pps_out <= pps_duty_high? pps_out_enb : 1'b0;
-        pps_int <= pps_duty_high? 1'b1 : 1'b0;
     end
 
    /////////////////////////////////////////////////////////////////////////////////
@@ -415,8 +404,8 @@ module x300_core
       .SFPP1_ModAbs(SFPP1_ModAbs),.SFPP1_TxFault(SFPP1_TxFault),.SFPP1_RxLOS(SFPP1_RxLOS),
       .SFPP1_RS0(SFPP1_RS0), .SFPP1_RS1(SFPP1_RS1),
       //clocky locky misc
-      .clock_status({LMK_Holdover, LMK_Lock, LMK_Status}),
+      .clock_status({pps_detect, LMK_Holdover, LMK_Lock, LMK_Status}),
-      .clock_control({clock_misc_opt[1:0], pps_out_enb, pps_select, clock_ref_sel[1:0]}),
+      .clock_control({clock_misc_opt[1:0], pps_out_enb, pps_select[1:0], clock_ref_sel[1:0]}),
       // Eth0
       .eth0_tx_tdata(eth0_tx_tdata), .eth0_tx_tuser(eth0_tx_tuser), .eth0_tx_tlast(eth0_tx_tlast),
       .eth0_tx_tvalid(eth0_tx_tvalid), .eth0_tx_tready(eth0_tx_tready),
@@ -557,7 +546,7 @@ module x300_core
       .tx_tvalid_bo(r0_tx_tvalid_bo), .tx_tready_bo(r0_tx_tready_bo),
       .tx_tdata_bi(r0_tx_tdata_bi), .tx_tlast_bi(r0_tx_tlast_bi),
       .tx_tvalid_bi(r0_tx_tvalid_bi), .tx_tready_bi(r0_tx_tready_bi),
-      .pps(pps_int), .sync_dacs(sync_dacs_radio0)
+      .pps(pps_del[1]), .sync_dacs(sync_dacs_radio0)
       );
 
      always @(posedge radio_clk)
@@ -590,7 +579,7 @@ module x300_core
       .tx_tvalid_bo(r1_tx_tvalid_bo), .tx_tready_bo(r1_tx_tready_bo),
       .tx_tdata_bi(r1_tx_tdata_bi), .tx_tlast_bi(r1_tx_tlast_bi),
       .tx_tvalid_bi(r1_tx_tvalid_bi), .tx_tready_bi(r1_tx_tready_bi),
-      .pps(pps_int), .sync_dacs(sync_dacs_radio1)
+      .pps(pps_del[1]), .sync_dacs(sync_dacs_radio1)
       );
 
    always @(posedge radio_clk)