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x300 fpga: updating FPGA code with latest bug fixes

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Original-commit: 847b7a631f5e73d732c88a4b4aa91595cf4e4a07
This commit is contained in:
Ben Hilburn
2014-03-20 16:08:24 -07:00
parent 864a1718c5
commit 8f1cfd55b1
6 changed files with 3455 additions and 3434 deletions
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top/x300/x300_core.v
+33 -44
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@@ -104,9 +104,9 @@ module x300_core
`endif // !`ifdef
// Time
input gps_pps,
input ext_pps,
output reg pps_out,
input pps,
output [1:0] pps_select,
output pps_out_enb,
output gps_txd,
input gps_rxd,
// Debug UART
@@ -369,31 +369,20 @@ module x300_core
/////////////////////////////////////////////////////////////////////////////////
// PPS synchronization and generation logic
// PPS synchronization logic
/////////////////////////////////////////////////////////////////////////////////
//PPS input signals will be flopped in via the 10MHz reference clock.
//Its assumed that the radio clock, which is derived from the 10MHz,
//will be able to flop this captured PPS signal without metastability.
//And that the relation of the radio clock to this ref clock will be
//consistent enough across multiple units to use for this purpose.
reg [1:0] ext_pps_del, gps_pps_del;
always @(posedge ext_ref_clk) ext_pps_del[1:0] <= {ext_pps_del[0], ext_pps};
always @(posedge ext_ref_clk) gps_pps_del[1:0] <= {gps_pps_del[0], gps_pps};
reg [1:0] pps_del;
always @(posedge ext_ref_clk) pps_del[1:0] <= {pps_del[0], pps};
//Generate a PPS signal disciplined by the input reference PPS.
//The PPS signal is 25% duty cycle, and generated by the rising edge.
reg pps_int;
wire pps_out_enb, pps_select;
reg [31:0] pps_count;
wire pps_duty_high = (pps_count < 32'd2500000);
wire pps_edge = pps_select? (ext_pps_del == 2'b01) : (gps_pps_del == 2'b01);
//PPS detection - toggle pps_detect on each PPS rising edge.
reg pps_detect;
always @(posedge ext_ref_clk) begin
if (pps_edge) pps_count <= 32'd3; //delay = sampling + detection + flopping out
else if (pps_count == 32'd9999999) pps_count <= 32'b0;
else pps_count <= pps_count + 1'b1;
pps_out <= pps_duty_high? pps_out_enb : 1'b0;
pps_int <= pps_duty_high? 1'b1 : 1'b0;
if (pps_del == 2'b01) pps_detect <= ~pps_detect;
end
/////////////////////////////////////////////////////////////////////////////////
@@ -415,8 +404,8 @@ module x300_core
.SFPP1_ModAbs(SFPP1_ModAbs),.SFPP1_TxFault(SFPP1_TxFault),.SFPP1_RxLOS(SFPP1_RxLOS),
.SFPP1_RS0(SFPP1_RS0), .SFPP1_RS1(SFPP1_RS1),
//clocky locky misc
.clock_status({LMK_Holdover, LMK_Lock, LMK_Status}),
.clock_control({clock_misc_opt[1:0], pps_out_enb, pps_select, clock_ref_sel[1:0]}),
.clock_status({pps_detect, LMK_Holdover, LMK_Lock, LMK_Status}),
.clock_control({clock_misc_opt[1:0], pps_out_enb, pps_select[1:0], clock_ref_sel[1:0]}),
// Eth0
.eth0_tx_tdata(eth0_tx_tdata), .eth0_tx_tuser(eth0_tx_tuser), .eth0_tx_tlast(eth0_tx_tlast),
.eth0_tx_tvalid(eth0_tx_tvalid), .eth0_tx_tready(eth0_tx_tready),
@@ -557,7 +546,7 @@ module x300_core
.tx_tvalid_bo(r0_tx_tvalid_bo), .tx_tready_bo(r0_tx_tready_bo),
.tx_tdata_bi(r0_tx_tdata_bi), .tx_tlast_bi(r0_tx_tlast_bi),
.tx_tvalid_bi(r0_tx_tvalid_bi), .tx_tready_bi(r0_tx_tready_bi),
.pps(pps_int), .sync_dacs(sync_dacs_radio0)
.pps(pps_del[1]), .sync_dacs(sync_dacs_radio0)
);
always @(posedge radio_clk)
@@ -590,7 +579,7 @@ module x300_core
.tx_tvalid_bo(r1_tx_tvalid_bo), .tx_tready_bo(r1_tx_tready_bo),
.tx_tdata_bi(r1_tx_tdata_bi), .tx_tlast_bi(r1_tx_tlast_bi),
.tx_tvalid_bi(r1_tx_tvalid_bi), .tx_tready_bi(r1_tx_tready_bi),
.pps(pps_int), .sync_dacs(sync_dacs_radio1)
.pps(pps_del[1]), .sync_dacs(sync_dacs_radio1)
);
always @(posedge radio_clk)
@@ -987,7 +976,7 @@ module x300_core
//
.debug()
);
axi_dram_fifo
#(.BASE('h2000000),
.SIZE(24),
@@ -1107,15 +1096,15 @@ module x300_core
// Alternate smaller internal SRAM based FIFO's for Tx when DRAM not compiled into FPGA.
// Short FIFO's added for ease of timing closure since large FIFO's spread all over die.
//
wire [63:0] r0_tx_tdata_bos; wire r0_tx_tlast_bos, r0_tx_tvalid_bos, r0_tx_tready_bos;
wire [63:0] r0_tx_tdata_bos; wire r0_tx_tlast_bos, r0_tx_tvalid_bos, r0_tx_tready_bos;
wire [63:0] r0_tx_tdata_0; wire r0_tx_tlast_0, r0_tx_tvalid_0, r0_tx_tready_0;
wire [63:0] r0_tx_tdata_0s; wire r0_tx_tlast_0s, r0_tx_tvalid_0s, r0_tx_tready_0s;
wire [63:0] r0_tx_tdata_0s; wire r0_tx_tlast_0s, r0_tx_tvalid_0s, r0_tx_tready_0s;
wire [63:0] r0_tx_tdata_1; wire r0_tx_tlast_1, r0_tx_tvalid_1, r0_tx_tready_1;
wire [63:0] r0_tx_tdata_1s; wire r0_tx_tlast_1s, r0_tx_tvalid_1s, r0_tx_tready_1s;
wire [63:0] r0_tx_tdata_1s; wire r0_tx_tlast_1s, r0_tx_tvalid_1s, r0_tx_tready_1s;
wire [63:0] r0_tx_tdata_2; wire r0_tx_tlast_2, r0_tx_tvalid_2, r0_tx_tready_2;
wire [63:0] r0_tx_tdata_2s; wire r0_tx_tlast_2s, r0_tx_tvalid_2s, r0_tx_tready_2s;
wire [63:0] r0_tx_tdata_bis; wire r0_tx_tlast_bis, r0_tx_tvalid_bis, r0_tx_tready_bis;
axi_fifo_short #(.WIDTH(65)) tx_fifo0_bos
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1137,7 +1126,7 @@ module x300_core
.o_tdata({r0_tx_tlast_0s,r0_tx_tdata_0s}), .o_tvalid(r0_tx_tvalid_0s), .o_tready(r0_tx_tready_0s),
.space(), .occupied()
);
axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_1
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({r0_tx_tlast_0s,r0_tx_tdata_0s}), .i_tvalid(r0_tx_tvalid_0s), .i_tready(r0_tx_tready_0s),
@@ -1151,13 +1140,13 @@ module x300_core
.o_tdata({r0_tx_tlast_1s,r0_tx_tdata_1s}), .o_tvalid(r0_tx_tvalid_1s), .o_tready(r0_tx_tready_1s),
.space(), .occupied()
);
axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_2
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({r0_tx_tlast_1s,r0_tx_tdata_1s}), .i_tvalid(r0_tx_tvalid_1s), .i_tready(r0_tx_tready_1s),
.o_tdata({r0_tx_tlast_2,r0_tx_tdata_2}), .o_tvalid(r0_tx_tvalid_2), .o_tready(r0_tx_tready_2),
.space(), .occupied());
axi_fifo_short #(.WIDTH(65)) tx_fifo0_2s
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1165,13 +1154,13 @@ module x300_core
.o_tdata({r0_tx_tlast_2s,r0_tx_tdata_2s}), .o_tvalid(r0_tx_tvalid_2s), .o_tready(r0_tx_tready_2s),
.space(), .occupied()
);
axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_3
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({r0_tx_tlast_2s,r0_tx_tdata_2s}), .i_tvalid(r0_tx_tvalid_2s), .i_tready(r0_tx_tready_2s),
.o_tdata({r0_tx_tlast_bis,r0_tx_tdata_bis}), .o_tvalid(r0_tx_tvalid_bis), .o_tready(r0_tx_tready_bis),
.space(), .occupied());
axi_fifo_short #(.WIDTH(65)) tx_fifo0_bis
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1180,15 +1169,15 @@ module x300_core
.space(), .occupied()
);
wire [63:0] r1_tx_tdata_bos; wire r1_tx_tlast_bos, r1_tx_tvalid_bos, r1_tx_tready_bos;
wire [63:0] r1_tx_tdata_bos; wire r1_tx_tlast_bos, r1_tx_tvalid_bos, r1_tx_tready_bos;
wire [63:0] r1_tx_tdata_0; wire r1_tx_tlast_0, r1_tx_tvalid_0, r1_tx_tready_0;
wire [63:0] r1_tx_tdata_0s; wire r1_tx_tlast_0s, r1_tx_tvalid_0s, r1_tx_tready_0s;
wire [63:0] r1_tx_tdata_0s; wire r1_tx_tlast_0s, r1_tx_tvalid_0s, r1_tx_tready_0s;
wire [63:0] r1_tx_tdata_1; wire r1_tx_tlast_1, r1_tx_tvalid_1, r1_tx_tready_1;
wire [63:0] r1_tx_tdata_1s; wire r1_tx_tlast_1s, r1_tx_tvalid_1s, r1_tx_tready_1s;
wire [63:0] r1_tx_tdata_1s; wire r1_tx_tlast_1s, r1_tx_tvalid_1s, r1_tx_tready_1s;
wire [63:0] r1_tx_tdata_2; wire r1_tx_tlast_2, r1_tx_tvalid_2, r1_tx_tready_2;
wire [63:0] r1_tx_tdata_2s; wire r1_tx_tlast_2s, r1_tx_tvalid_2s, r1_tx_tready_2s;
wire [63:0] r1_tx_tdata_bis; wire r1_tx_tlast_bis, r1_tx_tvalid_bis, r1_tx_tready_bis;
axi_fifo_short #(.WIDTH(65)) tx_fifo1_bos
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1210,7 +1199,7 @@ module x300_core
.o_tdata({r1_tx_tlast_0s,r1_tx_tdata_0s}), .o_tvalid(r1_tx_tvalid_0s), .o_tready(r1_tx_tready_0s),
.space(), .occupied()
);
axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo1_1
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({r1_tx_tlast_0s,r1_tx_tdata_0s}), .i_tvalid(r1_tx_tvalid_0s), .i_tready(r1_tx_tready_0s),
@@ -1224,13 +1213,13 @@ module x300_core
.o_tdata({r1_tx_tlast_1s,r1_tx_tdata_1s}), .o_tvalid(r1_tx_tvalid_1s), .o_tready(r1_tx_tready_1s),
.space(), .occupied()
);
axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo1_2
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({r1_tx_tlast_1s,r1_tx_tdata_1s}), .i_tvalid(r1_tx_tvalid_1s), .i_tready(r1_tx_tready_1s),
.o_tdata({r1_tx_tlast_2,r1_tx_tdata_2}), .o_tvalid(r1_tx_tvalid_2), .o_tready(r1_tx_tready_2),
.space(), .occupied());
axi_fifo_short #(.WIDTH(65)) tx_fifo1_2s
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1238,13 +1227,13 @@ module x300_core
.o_tdata({r1_tx_tlast_2s,r1_tx_tdata_2s}), .o_tvalid(r1_tx_tvalid_2s), .o_tready(r1_tx_tready_2s),
.space(), .occupied()
);
axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo1_3
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({r1_tx_tlast_2s,r1_tx_tdata_2s}), .i_tvalid(r1_tx_tvalid_2s), .i_tready(r1_tx_tready_2s),
.o_tdata({r1_tx_tlast_bis,r1_tx_tdata_bis}), .o_tvalid(r1_tx_tvalid_bis), .o_tready(r1_tx_tready_bis),
.space(), .occupied());
axi_fifo_short #(.WIDTH(65)) tx_fifo1_bis
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1254,7 +1243,7 @@ module x300_core
);
`endif // `ifndef NO_DRAM_FIFOS
//