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x300 fpga: updating FPGA code with latest bug fixes

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Original-commit: 847b7a631f5e73d732c88a4b4aa91595cf4e4a07
This commit is contained in:
Ben Hilburn
2014-03-20 16:08:24 -07:00
parent 864a1718c5
commit 8f1cfd55b1
6 changed files with 3455 additions and 3434 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x300/bus_int.v
+6 -6
View File
@@ -43,8 +43,8 @@ module bus_int
inout SFPP1_RS0,
inout SFPP1_RS1,
//
input [3:0] clock_status,
output [5:0] clock_control,
input [4:0] clock_status,
output [6:0] clock_control,
// ETH0
output [63:0] eth0_tx_tdata, output [3:0] eth0_tx_tuser, output eth0_tx_tlast, output eth0_tx_tvalid, input eth0_tx_tready,
input [63:0] eth0_rx_tdata, input [3:0] eth0_rx_tuser, input eth0_rx_tlast, input eth0_rx_tvalid, output eth0_rx_tready,
@@ -141,7 +141,7 @@ module bus_int
localparam RB_BIST = 8'd128;
localparam COMPAT_MAJOR = 16'h0003;
localparam COMPAT_MAJOR = 16'h0004;
localparam COMPAT_MINOR = 16'h0000;
wire [31:0] set_data;
@@ -295,8 +295,8 @@ module bus_int
.strobe(set_stb), .addr(set_addr), .in(set_data),
.out(sw_rst));
setting_reg #(.my_addr(SR_CLOCK_CTRL), .awidth(SR_AWIDTH), .width(6),
.at_reset(6'b100000) //bit 5 high means GPSDO on by default
setting_reg #(.my_addr(SR_CLOCK_CTRL), .awidth(SR_AWIDTH), .width(7),
.at_reset(7'b1000000) //bit 6 high means GPSDO on by default
) set_clk_ctrl
(.clk(clk), .rst(reset),
.strobe(set_stb), .addr(set_addr), .in(set_data),
@@ -341,7 +341,7 @@ module bus_int
RB_COUNTER: rb_data = counter;
RB_SPI_RDY: rb_data = {31'b0, spi_ready};
RB_SPI_DATA: rb_data = rb_spi_data;
RB_CLK_STATUS: rb_data = {28'b0, clock_status};
RB_CLK_STATUS: rb_data = {27'b0, clock_status};
// SFPP Interface pins.
RB_SFPP_STATUS0: rb_data = {26'b0,SFPP0_ModAbs_chgd,SFPP0_TxFault_chgd,SFPP0_RxLOS_chgd,
SFPP0_ModAbs_reg2,SFPP0_TxFault_reg2,SFPP0_RxLOS_reg2};
top/x300/capture_ddrlvds.v
+14 -14
View File
@@ -7,7 +7,7 @@
module capture_ddrlvds
#(parameter WIDTH=7,
parameter B250=0)
parameter X300=0)
(input clk,
input reset,
input ssclk_p,
@@ -20,15 +20,15 @@ module capture_ddrlvds
wire ssclk;
wire [(2*WIDTH)-1:0] out_pre1;
wire ssclk_bufio1, ssclk_bufio2, ssclk_bufr, ssclk_bufmr;
IBUFGDS #(.DIFF_TERM("TRUE"))
IBUFGDS #(.DIFF_TERM("TRUE"))
clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
BUFMR clkbufmr (
.I(ssclk),
.O(ssclk_bufmr)
);
BUFIO clkbufio1 (
.I(ssclk_bufmr),
.O(ssclk_bufio1)
@@ -37,22 +37,22 @@ module capture_ddrlvds
.I(ssclk_bufmr),
.O(ssclk_bufio2)
);
BUFR
BUFR
#(.SIM_DEVICE("7SERIES"),
.BUFR_DIVIDE("BYPASS"))
clkbufr (
.I(ssclk_bufmr),
.O(ssclk_bufr)
);
genvar i;
generate
for(i = 0; i < WIDTH; i = i + 1)
begin : gen_lvds_pins
if ((i == 10) && (B250 == 1)) begin
if ((i == 10) && (X300 == 1)) begin
IBUFDS #(.DIFF_TERM("FALSE")) ibufds
(.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) );
IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) iddr
@@ -68,12 +68,12 @@ module capture_ddrlvds
end
endgenerate
reg rd_en;
wire full, empty, almost_empty;
input_sample_fifo input_sample_fifo_i
(
.rst(reset), // input rst
@@ -88,7 +88,7 @@ module capture_ddrlvds
.almost_empty(almost_empty) // output almost_empty
);
always @(posedge clk) begin
if (reset)
rd_en <= 0;
top/x300/coregen/bootram.coe
+3332 -3332
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File diff suppressed because it is too large Load Diff
top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v
+28 -28
View File
@@ -4,13 +4,13 @@
//-----------------------------------------------------------------------------
// File : ten_gig_eth_pcs_pma_example_design.v
//-----------------------------------------------------------------------------
// Description: This file is a wrapper for the 10GBASE-R core; it contains all
// Description: This file is a wrapper for the 10GBASE-R core; it contains all
// of the clock buffers required for implementing the block level
//-----------------------------------------------------------------------------
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
@@ -62,7 +62,7 @@ module ten_gig_eth_pcs_pma_x300_top
// input refclk_p,
// input refclk_n,
input refclk156,
input refclk156_buf,
input refclk156_buf,
output clk156,
input reset,
input [63 : 0] xgmii_txd,
@@ -87,37 +87,37 @@ module ten_gig_eth_pcs_pma_x300_top
// Signal declarations
wire clk156;
// Sync the global reset to the relevant clocks
reg core_reset_tx;
reg core_reset_rx;
reg txreset322;
reg rxreset322;
reg dclk_reset;
reg core_reset_tx_tmp;
reg core_reset_rx_tmp;
reg txreset322_tmp;
reg rxreset322_tmp;
reg dclk_reset_tmp;
(* KEEP = "true" *)
wire txclk322;
wire rxclk322;
wire dclk;
wire tx_resetdone_int;
wire rx_resetdone_int;
reg [63:0] xgmii_txd_reg;
reg [7:0] xgmii_txc_reg;
wire [63:0] xgmii_rxd_int;
wire [7:0] xgmii_rxc_int;
wire mdio_out_int;
wire mdio_tri_int;
assign resetdone = tx_resetdone_int && rx_resetdone_int;
//synthesis attribute async_reg of core_reset_tx_tmp is "true";
//synthesis attribute async_reg of core_reset_tx is "true";
//synthesis attribute async_reg of core_reset_rx_tmp is "true";
@@ -135,19 +135,19 @@ module ten_gig_eth_pcs_pma_x300_top
begin
// Hold core in reset until everything else is ready...
// IJB. Per AR# 53443 changed these lines:
// core_reset_tx_tmp <= (!(tx_resetdone_int) || reset ||
// core_reset_tx_tmp <= (!(tx_resetdone_int) || reset ||
// tx_fault || !(signal_detect) );
core_reset_tx_tmp <= (!(tx_resetdone_int) || reset);
core_reset_tx <= core_reset_tx_tmp;
// core_reset_rx_tmp <= (!(rx_resetdone_int) || reset ||
// core_reset_rx_tmp <= (!(rx_resetdone_int) || reset ||
// tx_fault || !(signal_detect) );
core_reset_rx_tmp <= (!(rx_resetdone_int) || reset || !(signal_detect));
core_reset_rx <= core_reset_rx_tmp;
end
end
end
//synthesis attribute async_reg of txreset322_tmp is "true";
//synthesis attribute async_reg of txreset322 is "true";
always @(posedge reset or posedge txclk322)
@@ -163,7 +163,7 @@ module ten_gig_eth_pcs_pma_x300_top
txreset322 <= txreset322_tmp;
end
end
//synthesis attribute async_reg of rxreset322_tmp is "true";
//synthesis attribute async_reg of rxreset322 is "true";
always @(posedge reset or posedge rxclk322)
@@ -179,7 +179,7 @@ module ten_gig_eth_pcs_pma_x300_top
rxreset322 <= rxreset322_tmp;
end
end
//synthesis attribute async_reg of dclk_reset_tmp is "true";
//synthesis attribute async_reg of dclk_reset is "true";
always @(posedge reset or posedge dclk)
@@ -194,28 +194,28 @@ module ten_gig_eth_pcs_pma_x300_top
dclk_reset_tmp <= core_reset_rx;
dclk_reset <= dclk_reset_tmp;
end
end
end
// Add a pipeline to the xmgii_tx inputs, to aid timing closure
always @(posedge clk156)
begin
xgmii_txd_reg <= xgmii_txd;
xgmii_txc_reg <= xgmii_txc;
xgmii_txd_reg <= xgmii_txd;
xgmii_txc_reg <= xgmii_txc;
end
// Add a pipeline to the xmgii_rx outputs, to aid timing closure
always @(posedge clk156)
begin
xgmii_rxd <= xgmii_rxd_int;
xgmii_rxc <= xgmii_rxc_int;
xgmii_rxd <= xgmii_rxd_int;
xgmii_rxc <= xgmii_rxc_int;
end
// Add a pipeline to the mdio outputs, to aid timing closure
// This is safe because the mdio clock is running so slowly
always @(posedge clk156)
begin
mdio_out <= mdio_out_int;
mdio_tri <= mdio_tri_int;
mdio_out <= mdio_out_int;
mdio_tri <= mdio_tri_int;
end
// Instantiate the 10GBASE-R Block Level
@@ -256,10 +256,10 @@ module ten_gig_eth_pcs_pma_x300_top
.signal_detect(signal_detect),
.tx_fault(tx_fault),
.tx_disable(tx_disable));
// assign core_clk156_out = clk156;
// Not needed in B250
// Not needed in X300
/* -----\/----- EXCLUDED -----\/-----
ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) rx_clk_ddr(
top/x300/x300.v
+42 -10
View File
@@ -314,13 +314,13 @@ module x300
//////////////////////////////////////////////////////////////////////
// CPRI Clock output -- this is the dirty recovered clock from the MGT
// This goes to the LMK04816 which locks to it and cleans it up
// We get the clean versions back as CPRI_CLK (for the CPRI MGT)
// We get the clean versions back as CPRI_CLK (for the CPRI MGT)
// and FPGA_CLK (for our main rfclk)
//////////////////////////////////////////////////////////////////////
wire cpri_clk_out = 1'b0; // FIXME - connect to CPRI clock recovery when implemented
OBUFDS OBUFDS_cpri (.I(cpri_clk_out), .O(CPRI_CLK_OUT_P), .OB(CPRI_CLK_OUT_N));
/////////////////////////////////////////////////////////////////////
//
// power-on-reset logic.
@@ -365,7 +365,7 @@ module x300
// after programming the AD9610.
//
////////////////////////////////////////////////////////////////////
reset_sync radio_reset_sync
(
.clk(radio_clk),
@@ -381,8 +381,40 @@ module x300
);
////////////////////////////////////////////////////////////////////
// PPS
// Support for internal, external, and GPSDO PPS inputs
// Every attempt to minimize propagation between the external PPS
// input and outputs to support daisy-chaining the signal.
////////////////////////////////////////////////////////////////////
// Generate an internal PPS signal with a 25% duty cycle
reg [31:0] pps_count;
wire int_pps = (pps_count < 32'd2500000);
always @(posedge ref_clk_10mhz) begin
if (pps_count >= 32'd9999999)
pps_count <= 32'b0;
else
pps_count <= pps_count + 1'b1;
end
// PPS MUX - selects internal, external, or gpsdo PPS
reg pps;
wire [1:0] pps_select;
wire pps_out_enb;
always @(*) begin
case(pps_select)
2'b00 : pps = EXT_PPS_IN;
2'b01 : pps = 1'b0;
2'b10 : pps = int_pps;
2'b11 : pps = GPS_PPS_OUT;
default: pps = 1'b0;
endcase
end
// PPS out and LED
assign EXT_PPS_OUT = pps & pps_out_enb;
assign LED_PPS = ~pps; // active low LED driver
assign LED_PPS = ~(GPS_PPS_OUT | EXT_PPS_IN);
assign LED_GPSLOCK = ~GPS_LOCK_OK;
assign LED_REFLOCK = ~LMK_Lock;
assign {LED_RX1_RX,LED_TXRX1_TX,LED_TXRX1_RX} = ~led0; // active low LED driver
@@ -451,7 +483,7 @@ module x300
// Analog diff pairs on I side of ADC are inverted for layout reasons, but data diff pairs are all swapped as well
// so I gets a double negative, and is unchanged. Q must be inverted.
capture_ddrlvds #(.WIDTH(14),.B250(1)) cap_db0
capture_ddrlvds #(.WIDTH(14),.X300(1)) cap_db0
(.clk(radio_clk), .reset(radio_rst), .ssclk_p(DB0_ADC_DCLK_P), .ssclk_n(DB0_ADC_DCLK_N),
.in_p({{DB0_ADC_DA6_P, DB0_ADC_DA5_P, DB0_ADC_DA4_P, DB0_ADC_DA3_P, DB0_ADC_DA2_P, DB0_ADC_DA1_P, DB0_ADC_DA0_P},
{DB0_ADC_DB6_P, DB0_ADC_DB5_P, DB0_ADC_DB4_P, DB0_ADC_DB3_P, DB0_ADC_DB2_P, DB0_ADC_DB1_P, DB0_ADC_DB0_P}}),
@@ -461,7 +493,7 @@ module x300
.out({rx0_i,rx0_q_inv}));
assign rx0[31:0] = { rx0_i, 2'b00, ~rx0_q_inv, 2'b00 };
capture_ddrlvds #(.WIDTH(14),.B250(1)) cap_db1
capture_ddrlvds #(.WIDTH(14),.X300(1)) cap_db1
(.clk(radio_clk), .reset(radio_rst), .ssclk_p(DB1_ADC_DCLK_P), .ssclk_n(DB1_ADC_DCLK_N),
.in_p({{DB1_ADC_DA6_P, DB1_ADC_DA5_P, DB1_ADC_DA4_P, DB1_ADC_DA3_P, DB1_ADC_DA2_P, DB1_ADC_DA1_P, DB1_ADC_DA0_P},
{DB1_ADC_DB6_P, DB1_ADC_DB5_P, DB1_ADC_DB4_P, DB1_ADC_DB3_P, DB1_ADC_DB2_P, DB1_ADC_DB1_P, DB1_ADC_DB0_P}}),
@@ -470,7 +502,7 @@ module x300
{DB1_ADC_DB6_N, DB1_ADC_DB5_N, DB1_ADC_DB4_N, DB1_ADC_DB3_N, DB1_ADC_DB2_N, DB1_ADC_DB1_N, DB1_ADC_DB0_N}}),
.out({rx1_i,rx1_q_inv}));
assign rx1[31:0] = { rx1_i, 2'b00, ~rx1_q_inv, 2'b00 };
/////////////////////////////////////////////////////////////////////
//
// DAC Interface for AD9146
@@ -1756,7 +1788,7 @@ module x300
///////////////////////////////////////////////////////////////////////////////////
//
// B250 Core
// X300 Core
//
///////////////////////////////////////////////////////////////////////////////////
x300_core x300_core
@@ -1836,10 +1868,10 @@ module x300
.gmii_txd1(gmii_txd1), .gmii_tx_en1(gmii_tx_en1), .gmii_tx_er1(gmii_tx_er1),
.gmii_rxd1(gmii_rxd1), .gmii_rx_dv1(gmii_rx_dv1), .gmii_rx_er1(gmii_rx_er1),
`endif // !`ifdef
// Time
.pps(pps),.pps_select(pps_select), .pps_out_enb(pps_out_enb),
// GPS Signals
.gps_pps(GPS_PPS_OUT), .ext_pps(EXT_PPS_IN),
.gps_txd(GPS_SER_IN), .gps_rxd(GPS_SER_OUT),
.pps_out(EXT_PPS_OUT),
// Debug UART
.debug_rxd(debug_rxd), .debug_txd(debug_txd),
// Misc.
top/x300/x300_core.v
+33 -44
View File
@@ -104,9 +104,9 @@ module x300_core
`endif // !`ifdef
// Time
input gps_pps,
input ext_pps,
output reg pps_out,
input pps,
output [1:0] pps_select,
output pps_out_enb,
output gps_txd,
input gps_rxd,
// Debug UART
@@ -369,31 +369,20 @@ module x300_core
/////////////////////////////////////////////////////////////////////////////////
// PPS synchronization and generation logic
// PPS synchronization logic
/////////////////////////////////////////////////////////////////////////////////
//PPS input signals will be flopped in via the 10MHz reference clock.
//Its assumed that the radio clock, which is derived from the 10MHz,
//will be able to flop this captured PPS signal without metastability.
//And that the relation of the radio clock to this ref clock will be
//consistent enough across multiple units to use for this purpose.
reg [1:0] ext_pps_del, gps_pps_del;
always @(posedge ext_ref_clk) ext_pps_del[1:0] <= {ext_pps_del[0], ext_pps};
always @(posedge ext_ref_clk) gps_pps_del[1:0] <= {gps_pps_del[0], gps_pps};
reg [1:0] pps_del;
always @(posedge ext_ref_clk) pps_del[1:0] <= {pps_del[0], pps};
//Generate a PPS signal disciplined by the input reference PPS.
//The PPS signal is 25% duty cycle, and generated by the rising edge.
reg pps_int;
wire pps_out_enb, pps_select;
reg [31:0] pps_count;
wire pps_duty_high = (pps_count < 32'd2500000);
wire pps_edge = pps_select? (ext_pps_del == 2'b01) : (gps_pps_del == 2'b01);
//PPS detection - toggle pps_detect on each PPS rising edge.
reg pps_detect;
always @(posedge ext_ref_clk) begin
if (pps_edge) pps_count <= 32'd3; //delay = sampling + detection + flopping out
else if (pps_count == 32'd9999999) pps_count <= 32'b0;
else pps_count <= pps_count + 1'b1;
pps_out <= pps_duty_high? pps_out_enb : 1'b0;
pps_int <= pps_duty_high? 1'b1 : 1'b0;
if (pps_del == 2'b01) pps_detect <= ~pps_detect;
end
/////////////////////////////////////////////////////////////////////////////////
@@ -415,8 +404,8 @@ module x300_core
.SFPP1_ModAbs(SFPP1_ModAbs),.SFPP1_TxFault(SFPP1_TxFault),.SFPP1_RxLOS(SFPP1_RxLOS),
.SFPP1_RS0(SFPP1_RS0), .SFPP1_RS1(SFPP1_RS1),
//clocky locky misc
.clock_status({LMK_Holdover, LMK_Lock, LMK_Status}),
.clock_control({clock_misc_opt[1:0], pps_out_enb, pps_select, clock_ref_sel[1:0]}),
.clock_status({pps_detect, LMK_Holdover, LMK_Lock, LMK_Status}),
.clock_control({clock_misc_opt[1:0], pps_out_enb, pps_select[1:0], clock_ref_sel[1:0]}),
// Eth0
.eth0_tx_tdata(eth0_tx_tdata), .eth0_tx_tuser(eth0_tx_tuser), .eth0_tx_tlast(eth0_tx_tlast),
.eth0_tx_tvalid(eth0_tx_tvalid), .eth0_tx_tready(eth0_tx_tready),
@@ -557,7 +546,7 @@ module x300_core
.tx_tvalid_bo(r0_tx_tvalid_bo), .tx_tready_bo(r0_tx_tready_bo),
.tx_tdata_bi(r0_tx_tdata_bi), .tx_tlast_bi(r0_tx_tlast_bi),
.tx_tvalid_bi(r0_tx_tvalid_bi), .tx_tready_bi(r0_tx_tready_bi),
.pps(pps_int), .sync_dacs(sync_dacs_radio0)
.pps(pps_del[1]), .sync_dacs(sync_dacs_radio0)
);
always @(posedge radio_clk)
@@ -590,7 +579,7 @@ module x300_core
.tx_tvalid_bo(r1_tx_tvalid_bo), .tx_tready_bo(r1_tx_tready_bo),
.tx_tdata_bi(r1_tx_tdata_bi), .tx_tlast_bi(r1_tx_tlast_bi),
.tx_tvalid_bi(r1_tx_tvalid_bi), .tx_tready_bi(r1_tx_tready_bi),
.pps(pps_int), .sync_dacs(sync_dacs_radio1)
.pps(pps_del[1]), .sync_dacs(sync_dacs_radio1)
);
always @(posedge radio_clk)
@@ -987,7 +976,7 @@ module x300_core
//
.debug()
);
axi_dram_fifo
#(.BASE('h2000000),
.SIZE(24),
@@ -1107,15 +1096,15 @@ module x300_core
// Alternate smaller internal SRAM based FIFO's for Tx when DRAM not compiled into FPGA.
// Short FIFO's added for ease of timing closure since large FIFO's spread all over die.
//
wire [63:0] r0_tx_tdata_bos; wire r0_tx_tlast_bos, r0_tx_tvalid_bos, r0_tx_tready_bos;
wire [63:0] r0_tx_tdata_bos; wire r0_tx_tlast_bos, r0_tx_tvalid_bos, r0_tx_tready_bos;
wire [63:0] r0_tx_tdata_0; wire r0_tx_tlast_0, r0_tx_tvalid_0, r0_tx_tready_0;
wire [63:0] r0_tx_tdata_0s; wire r0_tx_tlast_0s, r0_tx_tvalid_0s, r0_tx_tready_0s;
wire [63:0] r0_tx_tdata_0s; wire r0_tx_tlast_0s, r0_tx_tvalid_0s, r0_tx_tready_0s;
wire [63:0] r0_tx_tdata_1; wire r0_tx_tlast_1, r0_tx_tvalid_1, r0_tx_tready_1;
wire [63:0] r0_tx_tdata_1s; wire r0_tx_tlast_1s, r0_tx_tvalid_1s, r0_tx_tready_1s;
wire [63:0] r0_tx_tdata_1s; wire r0_tx_tlast_1s, r0_tx_tvalid_1s, r0_tx_tready_1s;
wire [63:0] r0_tx_tdata_2; wire r0_tx_tlast_2, r0_tx_tvalid_2, r0_tx_tready_2;
wire [63:0] r0_tx_tdata_2s; wire r0_tx_tlast_2s, r0_tx_tvalid_2s, r0_tx_tready_2s;
wire [63:0] r0_tx_tdata_bis; wire r0_tx_tlast_bis, r0_tx_tvalid_bis, r0_tx_tready_bis;
axi_fifo_short #(.WIDTH(65)) tx_fifo0_bos
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1137,7 +1126,7 @@ module x300_core
.o_tdata({r0_tx_tlast_0s,r0_tx_tdata_0s}), .o_tvalid(r0_tx_tvalid_0s), .o_tready(r0_tx_tready_0s),
.space(), .occupied()
);
axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_1
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({r0_tx_tlast_0s,r0_tx_tdata_0s}), .i_tvalid(r0_tx_tvalid_0s), .i_tready(r0_tx_tready_0s),
@@ -1151,13 +1140,13 @@ module x300_core
.o_tdata({r0_tx_tlast_1s,r0_tx_tdata_1s}), .o_tvalid(r0_tx_tvalid_1s), .o_tready(r0_tx_tready_1s),
.space(), .occupied()
);
axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_2
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({r0_tx_tlast_1s,r0_tx_tdata_1s}), .i_tvalid(r0_tx_tvalid_1s), .i_tready(r0_tx_tready_1s),
.o_tdata({r0_tx_tlast_2,r0_tx_tdata_2}), .o_tvalid(r0_tx_tvalid_2), .o_tready(r0_tx_tready_2),
.space(), .occupied());
axi_fifo_short #(.WIDTH(65)) tx_fifo0_2s
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1165,13 +1154,13 @@ module x300_core
.o_tdata({r0_tx_tlast_2s,r0_tx_tdata_2s}), .o_tvalid(r0_tx_tvalid_2s), .o_tready(r0_tx_tready_2s),
.space(), .occupied()
);
axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_3
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({r0_tx_tlast_2s,r0_tx_tdata_2s}), .i_tvalid(r0_tx_tvalid_2s), .i_tready(r0_tx_tready_2s),
.o_tdata({r0_tx_tlast_bis,r0_tx_tdata_bis}), .o_tvalid(r0_tx_tvalid_bis), .o_tready(r0_tx_tready_bis),
.space(), .occupied());
axi_fifo_short #(.WIDTH(65)) tx_fifo0_bis
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1180,15 +1169,15 @@ module x300_core
.space(), .occupied()
);
wire [63:0] r1_tx_tdata_bos; wire r1_tx_tlast_bos, r1_tx_tvalid_bos, r1_tx_tready_bos;
wire [63:0] r1_tx_tdata_bos; wire r1_tx_tlast_bos, r1_tx_tvalid_bos, r1_tx_tready_bos;
wire [63:0] r1_tx_tdata_0; wire r1_tx_tlast_0, r1_tx_tvalid_0, r1_tx_tready_0;
wire [63:0] r1_tx_tdata_0s; wire r1_tx_tlast_0s, r1_tx_tvalid_0s, r1_tx_tready_0s;
wire [63:0] r1_tx_tdata_0s; wire r1_tx_tlast_0s, r1_tx_tvalid_0s, r1_tx_tready_0s;
wire [63:0] r1_tx_tdata_1; wire r1_tx_tlast_1, r1_tx_tvalid_1, r1_tx_tready_1;
wire [63:0] r1_tx_tdata_1s; wire r1_tx_tlast_1s, r1_tx_tvalid_1s, r1_tx_tready_1s;
wire [63:0] r1_tx_tdata_1s; wire r1_tx_tlast_1s, r1_tx_tvalid_1s, r1_tx_tready_1s;
wire [63:0] r1_tx_tdata_2; wire r1_tx_tlast_2, r1_tx_tvalid_2, r1_tx_tready_2;
wire [63:0] r1_tx_tdata_2s; wire r1_tx_tlast_2s, r1_tx_tvalid_2s, r1_tx_tready_2s;
wire [63:0] r1_tx_tdata_bis; wire r1_tx_tlast_bis, r1_tx_tvalid_bis, r1_tx_tready_bis;
axi_fifo_short #(.WIDTH(65)) tx_fifo1_bos
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1210,7 +1199,7 @@ module x300_core
.o_tdata({r1_tx_tlast_0s,r1_tx_tdata_0s}), .o_tvalid(r1_tx_tvalid_0s), .o_tready(r1_tx_tready_0s),
.space(), .occupied()
);
axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo1_1
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({r1_tx_tlast_0s,r1_tx_tdata_0s}), .i_tvalid(r1_tx_tvalid_0s), .i_tready(r1_tx_tready_0s),
@@ -1224,13 +1213,13 @@ module x300_core
.o_tdata({r1_tx_tlast_1s,r1_tx_tdata_1s}), .o_tvalid(r1_tx_tvalid_1s), .o_tready(r1_tx_tready_1s),
.space(), .occupied()
);
axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo1_2
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({r1_tx_tlast_1s,r1_tx_tdata_1s}), .i_tvalid(r1_tx_tvalid_1s), .i_tready(r1_tx_tready_1s),
.o_tdata({r1_tx_tlast_2,r1_tx_tdata_2}), .o_tvalid(r1_tx_tvalid_2), .o_tready(r1_tx_tready_2),
.space(), .occupied());
axi_fifo_short #(.WIDTH(65)) tx_fifo1_2s
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1238,13 +1227,13 @@ module x300_core
.o_tdata({r1_tx_tlast_2s,r1_tx_tdata_2s}), .o_tvalid(r1_tx_tvalid_2s), .o_tready(r1_tx_tready_2s),
.space(), .occupied()
);
axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo1_3
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({r1_tx_tlast_2s,r1_tx_tdata_2s}), .i_tvalid(r1_tx_tvalid_2s), .i_tready(r1_tx_tready_2s),
.o_tdata({r1_tx_tlast_bis,r1_tx_tdata_bis}), .o_tvalid(r1_tx_tvalid_bis), .o_tready(r1_tx_tready_bis),
.space(), .occupied());
axi_fifo_short #(.WIDTH(65)) tx_fifo1_bis
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1254,7 +1243,7 @@ module x300_core
);
`endif // `ifndef NO_DRAM_FIFOS
//