fpga: lib: redirect old ctrlport modules to interface based ones
Original-commit: bf294111b9f49efb6373908274bc8d31bb8cb11d
This commit is contained in:
Max Köhler
@@ -0,0 +1,157 @@
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//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_decoder_param
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//
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// Description:
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//
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// This block splits a single control port interface into multiple. It is
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// used when you have a single master that needs to access multiple slaves.
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// For example, a NoC block where the registers are implemented in multiple
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// submodules that must be read/written by a single NoC shell.
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//
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// This version also implements address decoding. The request is passed to a
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// slave only if the address falls within that slave's address space. Each
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// slave can have a unique base address and address space size. The address
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// space is broken up as follows.
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//
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// PORT_BASE[0*20 +: 20] = Port 0 base address
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// │ ┐
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// │ ├── 2**PORT_ADDR_W[0*32 +: 32] bytes for slave 0
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// │ ┘
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// .
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// .
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// PORT_BASE[1*20 +: 20] = Port 1 base address
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// │ ┐
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// │ ├── 2**PORT_ADDR_W[1*32 +: 32] bytes for slave 1
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// │ ┘
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// .
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// .
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//
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// When passed to the slave, the base address is stripped from the request
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// address so that only the PORT_ADDR_W-bit address is passed through.
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//
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// Parameters:
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//
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// NUM_SLAVES : The number of slaves to connect to a master.
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// PORT_BASE : Base addresses to use fore each slave. This is a
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// concatenation of 20-bit addresses, where the right-most
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// (least-significant) 20 bits corresponds to slave 0. Each
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// address must be a multiple of 2**PORT_ADDR_W, where
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// PORT_ADDR_W is the number of address bits allocated to that
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// slave.
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// PORT_ADDR_W : Number of address bits to allocate to each slave. This is a
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// concatenation of 32-bit integers, where the right-most
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// (least-significant) 32 bits corresponds to the address space
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// for slave 0.
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//
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module ctrlport_decoder_param
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import ctrlport_pkg::*;
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#(
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int NUM_SLAVES = 4,
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bit [CTRLPORT_ADDR_W*NUM_SLAVES-1:0] PORT_BASE = { 20'h300, 20'h200, 20'h100, 20'h000 },
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bit [ 32*NUM_SLAVES-1:0] PORT_ADDR_W = { 32'd8, 32'd8, 32'd8, 32'd8 }
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) (
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input logic ctrlport_clk,
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input logic ctrlport_rst,
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// Slave Interface
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input logic s_ctrlport_req_wr,
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input logic s_ctrlport_req_rd,
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input logic [ CTRLPORT_ADDR_W-1:0] s_ctrlport_req_addr,
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input logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_req_data,
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input logic [CTRLPORT_BYTE_EN_W-1:0] s_ctrlport_req_byte_en,
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input logic s_ctrlport_req_has_time,
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input logic [ CTRLPORT_TIME_W-1:0] s_ctrlport_req_time,
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output logic s_ctrlport_resp_ack,
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output logic [ CTRLPORT_STS_W-1:0] s_ctrlport_resp_status,
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output logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_resp_data,
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// Master Interfaces
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output logic [ NUM_SLAVES-1:0] m_ctrlport_req_wr,
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output logic [ NUM_SLAVES-1:0] m_ctrlport_req_rd,
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output logic [ CTRLPORT_ADDR_W*NUM_SLAVES-1:0] m_ctrlport_req_addr,
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output logic [ CTRLPORT_DATA_W*NUM_SLAVES-1:0] m_ctrlport_req_data,
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output logic [CTRLPORT_BYTE_EN_W*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
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output logic [ NUM_SLAVES-1:0] m_ctrlport_req_has_time,
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output logic [ CTRLPORT_TIME_W*NUM_SLAVES-1:0] m_ctrlport_req_time,
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input logic [ NUM_SLAVES-1:0] m_ctrlport_resp_ack,
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input logic [ CTRLPORT_STS_W*NUM_SLAVES-1:0] m_ctrlport_resp_status,
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input logic [ CTRLPORT_DATA_W*NUM_SLAVES-1:0] m_ctrlport_resp_data
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);
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import ctrlport_pkg::*;
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// calculate port base address and size
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typedef int int_array_t[NUM_SLAVES];
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function int_array_t calc_port_base();
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int_array_t base;
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for (int i = 0; i < NUM_SLAVES; i++) begin
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base[i] = PORT_BASE[i*20 +: 20];
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end
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return base;
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endfunction
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function int_array_t calc_port_size();
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int_array_t size;
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for (int i = 0; i < NUM_SLAVES; i++) begin
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size[i] = 2**PORT_ADDR_W[i*32 +: 32];
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end
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return size;
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endfunction
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localparam int PORT_BASE_INT [NUM_SLAVES] = calc_port_base();
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localparam int PORT_SIZE_INT [NUM_SLAVES] = calc_port_size();
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// Define interfaces
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ctrlport_if s_ctrlport_if(.clk(ctrlport_clk), .rst(ctrlport_rst));
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ctrlport_if m_ctrlport_if[NUM_SLAVES](.clk(ctrlport_clk), .rst(ctrlport_rst));
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// Map existing ports to ctrlport_if
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always_comb begin
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s_ctrlport_if.req = '0;
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s_ctrlport_if.req.wr = s_ctrlport_req_wr;
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s_ctrlport_if.req.rd = s_ctrlport_req_rd;
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s_ctrlport_if.req.addr = s_ctrlport_req_addr;
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s_ctrlport_if.req.data = s_ctrlport_req_data;
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s_ctrlport_if.req.byte_en = s_ctrlport_req_byte_en;
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s_ctrlport_if.req.has_time = s_ctrlport_req_has_time;
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s_ctrlport_if.req.timestamp = s_ctrlport_req_time;
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s_ctrlport_resp_ack = s_ctrlport_if.resp.ack;
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s_ctrlport_resp_status = s_ctrlport_if.resp.status;
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s_ctrlport_resp_data = s_ctrlport_if.resp.data;
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end
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// Instantiate ctrlport_if_decoder module
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ctrlport_if_decoder #(
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.NUM_SLAVES(NUM_SLAVES),
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.PORT_BASE(PORT_BASE_INT),
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.PORT_SIZE(PORT_SIZE_INT)
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) decoder_inst (
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.s_ctrlport(s_ctrlport_if),
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.m_ctrlport(m_ctrlport_if)
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);
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// Unpack ctrlport_if to output port
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for (genvar i = 0; i < NUM_SLAVES; i++) begin : output_gen
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always_comb begin
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m_ctrlport_req_wr[i] = m_ctrlport_if[i].req.wr;
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m_ctrlport_req_rd[i] = m_ctrlport_if[i].req.rd;
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m_ctrlport_req_addr[i*CTRLPORT_ADDR_W +: CTRLPORT_ADDR_W] = m_ctrlport_if[i].req.addr;
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m_ctrlport_req_data[i*CTRLPORT_DATA_W +: CTRLPORT_DATA_W] = m_ctrlport_if[i].req.data;
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m_ctrlport_req_byte_en[i*CTRLPORT_BYTE_EN_W +: CTRLPORT_BYTE_EN_W] = m_ctrlport_if[i].req.byte_en;
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m_ctrlport_req_has_time[i] = m_ctrlport_if[i].req.has_time;
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m_ctrlport_req_time[i*CTRLPORT_TIME_W +: CTRLPORT_TIME_W] = m_ctrlport_if[i].req.timestamp;
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m_ctrlport_if[i].resp.ack = m_ctrlport_resp_ack[i];
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m_ctrlport_if[i].resp.status = ctrlport_status_t'(m_ctrlport_resp_status[i*CTRLPORT_STS_W +: CTRLPORT_STS_W]);
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m_ctrlport_if[i].resp.data = m_ctrlport_resp_data[i*CTRLPORT_DATA_W +: CTRLPORT_DATA_W];
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end
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end
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endmodule
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