From 8dc5d3aeec934b0cd9a82f552bf34d4b7705c476 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Max=20K=C3=B6hler?= Date: Wed, 19 Mar 2025 10:20:46 +0100 Subject: [PATCH] fpga: lib: redirect old ctrlport modules to interface based ones Original-commit: bf294111b9f49efb6373908274bc8d31bb8cb11d --- lib/rfnoc/core/ctrlport_if.sv | 2 +- lib/rfnoc/utils/Makefile.srcs | 14 +- lib/rfnoc/utils/ctrlport_clk_cross.sv | 115 +++++++++ lib/rfnoc/utils/ctrlport_clk_cross.v | 184 --------------- lib/rfnoc/utils/ctrlport_combiner.sv | 125 ++++++++++ lib/rfnoc/utils/ctrlport_combiner.v | 270 ---------------------- lib/rfnoc/utils/ctrlport_decoder.sv | 135 +++++++++++ lib/rfnoc/utils/ctrlport_decoder.v | 154 ------------ lib/rfnoc/utils/ctrlport_decoder_param.sv | 157 +++++++++++++ lib/rfnoc/utils/ctrlport_decoder_param.v | 171 -------------- lib/rfnoc/utils/ctrlport_splitter.sv | 110 +++++++++ lib/rfnoc/utils/ctrlport_splitter.v | 130 ----------- lib/rfnoc/utils/ctrlport_terminator.sv | 62 +++++ lib/rfnoc/utils/ctrlport_terminator.v | 50 ---- lib/rfnoc/utils/ctrlport_window.sv | 109 +++++++++ lib/rfnoc/utils/ctrlport_window.v | 73 ------ 16 files changed, 821 insertions(+), 1040 deletions(-) create mode 100644 lib/rfnoc/utils/ctrlport_clk_cross.sv delete mode 100644 lib/rfnoc/utils/ctrlport_clk_cross.v create mode 100644 lib/rfnoc/utils/ctrlport_combiner.sv delete mode 100644 lib/rfnoc/utils/ctrlport_combiner.v create mode 100644 lib/rfnoc/utils/ctrlport_decoder.sv delete mode 100644 lib/rfnoc/utils/ctrlport_decoder.v create mode 100644 lib/rfnoc/utils/ctrlport_decoder_param.sv delete mode 100644 lib/rfnoc/utils/ctrlport_decoder_param.v create mode 100644 lib/rfnoc/utils/ctrlport_splitter.sv delete mode 100644 lib/rfnoc/utils/ctrlport_splitter.v create mode 100644 lib/rfnoc/utils/ctrlport_terminator.sv delete mode 100644 lib/rfnoc/utils/ctrlport_terminator.v create mode 100644 lib/rfnoc/utils/ctrlport_window.sv delete mode 100644 lib/rfnoc/utils/ctrlport_window.v diff --git a/lib/rfnoc/core/ctrlport_if.sv b/lib/rfnoc/core/ctrlport_if.sv index 9d1826a..fe36ed7 100644 --- a/lib/rfnoc/core/ctrlport_if.sv +++ b/lib/rfnoc/core/ctrlport_if.sv @@ -12,7 +12,7 @@ interface ctrlport_if ( input logic clk, - input logic rst = 1'b0 + input logic rst ); import ctrlport_pkg::*; diff --git a/lib/rfnoc/utils/Makefile.srcs b/lib/rfnoc/utils/Makefile.srcs index 322cdb6..b6a315b 100644 --- a/lib/rfnoc/utils/Makefile.srcs +++ b/lib/rfnoc/utils/Makefile.srcs @@ -17,19 +17,19 @@ context_handler_sync.v \ context_builder.v \ context_parser.v \ ctrlport_timer.v \ -ctrlport_combiner.v \ -ctrlport_decoder.v \ -ctrlport_decoder_param.v \ -ctrlport_window.v \ -ctrlport_splitter.v \ +ctrlport_combiner.sv \ +ctrlport_decoder.sv \ +ctrlport_decoder_param.sv \ +ctrlport_window.sv \ +ctrlport_splitter.sv \ ctrlport_resp_combine.v \ -ctrlport_clk_cross.v \ +ctrlport_clk_cross.sv \ ctrlport_reg_rw.v \ ctrlport_reg_ro.v \ ctrlport_to_settings_bus.v \ noc_shell_generic_ctrlport_pyld_chdr.v \ timekeeper.v \ -ctrlport_terminator.v \ +ctrlport_terminator.sv \ chdr_strip_header.sv \ ctrlport_if_clk_cross.sv \ ctrlport_if_combiner.sv \ diff --git a/lib/rfnoc/utils/ctrlport_clk_cross.sv b/lib/rfnoc/utils/ctrlport_clk_cross.sv new file mode 100644 index 0000000..e5b3e86 --- /dev/null +++ b/lib/rfnoc/utils/ctrlport_clk_cross.sv @@ -0,0 +1,115 @@ +// +// Copyright 2025 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: ctrlport_clk_cross +// +// Description: +// +// Crosses a CTRL Port request and response between two clock domains. +// + + +module ctrlport_clk_cross + import ctrlport_pkg::*; +( + input logic rst, // Can be either clock domain, but must be glitch-free + + //--------------------------------------------------------------------------- + // Input Clock Domain (Slave Interface) + //--------------------------------------------------------------------------- + + input logic s_ctrlport_clk, + input logic s_ctrlport_req_wr, + input logic s_ctrlport_req_rd, + input logic [ CTRLPORT_ADDR_W-1:0] s_ctrlport_req_addr, + input logic [ CTRLPORT_PORTID_W-1:0] s_ctrlport_req_portid, + input logic [CTRLPORT_REM_EPID_W-1:0] s_ctrlport_req_rem_epid, + input logic [ CTRLPORT_PORTID_W-1:0] s_ctrlport_req_rem_portid, + input logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_req_data, + input logic [ CTRLPORT_BYTE_EN_W-1:0] s_ctrlport_req_byte_en, + input logic s_ctrlport_req_has_time, + input logic [ CTRLPORT_TIME_W-1:0] s_ctrlport_req_time, + output logic s_ctrlport_resp_ack, + output logic [ CTRLPORT_STS_W-1:0] s_ctrlport_resp_status, + output logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_resp_data, + + //--------------------------------------------------------------------------- + // Output Clock Domain (Master Interface) + //--------------------------------------------------------------------------- + + input logic m_ctrlport_clk, + output logic m_ctrlport_req_wr, + output logic m_ctrlport_req_rd, + output logic [ CTRLPORT_ADDR_W-1:0] m_ctrlport_req_addr, + output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_portid, + output logic [CTRLPORT_REM_EPID_W-1:0] m_ctrlport_req_rem_epid, + output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_rem_portid, + output logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_req_data, + output logic [ CTRLPORT_BYTE_EN_W-1:0] m_ctrlport_req_byte_en, + output logic m_ctrlport_req_has_time, + output logic [ CTRLPORT_TIME_W-1:0] m_ctrlport_req_time, + input logic m_ctrlport_resp_ack, + input logic [ CTRLPORT_STS_W-1:0] m_ctrlport_resp_status, + input logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_resp_data +); + + import ctrlport_pkg::*; + + // Reset sync to both clock domains + logic m_rst, s_rst; + reset_sync slave_reset_sync_inst ( + .clk(s_ctrlport_clk), .reset_in(rst), .reset_out(s_rst) + ); + reset_sync master_reset_sync_inst ( + .clk(m_ctrlport_clk), .reset_in(rst), .reset_out(m_rst) + ); + + // Define interfaces + ctrlport_if s_ctrlport_if(.clk(s_ctrlport_clk), .rst(s_rst)); + ctrlport_if m_ctrlport_if(.clk(m_ctrlport_clk), .rst(m_rst)); + + // Map existing ports to ctrlport_if + always_comb begin + s_ctrlport_if.req.wr = s_ctrlport_req_wr; + s_ctrlport_if.req.rd = s_ctrlport_req_rd; + s_ctrlport_if.req.addr = s_ctrlport_req_addr; + s_ctrlport_if.req.port_id = s_ctrlport_req_portid; + s_ctrlport_if.req.remote_epid = s_ctrlport_req_rem_epid; + s_ctrlport_if.req.remote_portid = s_ctrlport_req_rem_portid; + s_ctrlport_if.req.data = s_ctrlport_req_data; + s_ctrlport_if.req.byte_en = s_ctrlport_req_byte_en; + s_ctrlport_if.req.has_time = s_ctrlport_req_has_time; + s_ctrlport_if.req.timestamp = s_ctrlport_req_time; + + s_ctrlport_resp_ack = s_ctrlport_if.resp.ack; + s_ctrlport_resp_status = s_ctrlport_if.resp.status; + s_ctrlport_resp_data = s_ctrlport_if.resp.data; + end + + // Instantiate ctrlport_if_clk_cross module + ctrlport_if_clk_cross clk_cross_inst ( + .s_ctrlport(s_ctrlport_if), + .m_ctrlport(m_ctrlport_if) + ); + + // Unpack ctrlport_if to output port + always_comb begin + m_ctrlport_req_wr = m_ctrlport_if.req.wr; + m_ctrlport_req_rd = m_ctrlport_if.req.rd; + m_ctrlport_req_addr = m_ctrlport_if.req.addr; + m_ctrlport_req_portid = m_ctrlport_if.req.port_id; + m_ctrlport_req_rem_epid = m_ctrlport_if.req.remote_epid; + m_ctrlport_req_rem_portid = m_ctrlport_if.req.remote_portid; + m_ctrlport_req_data = m_ctrlport_if.req.data; + m_ctrlport_req_byte_en = m_ctrlport_if.req.byte_en; + m_ctrlport_req_has_time = m_ctrlport_if.req.has_time; + m_ctrlport_req_time = m_ctrlport_if.req.timestamp; + + m_ctrlport_if.resp.ack = m_ctrlport_resp_ack; + m_ctrlport_if.resp.status = ctrlport_status_t'(m_ctrlport_resp_status); + m_ctrlport_if.resp.data = m_ctrlport_resp_data; + end + +endmodule diff --git a/lib/rfnoc/utils/ctrlport_clk_cross.v b/lib/rfnoc/utils/ctrlport_clk_cross.v deleted file mode 100644 index 3747481..0000000 --- a/lib/rfnoc/utils/ctrlport_clk_cross.v +++ /dev/null @@ -1,184 +0,0 @@ -// -// Copyright 2019 Ettus Research, a National Instruments Company -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: ctrlport_clk_cross -// -// Description: -// -// Crosses a CTRL Port request and response between two clock domains. -// - - -module ctrlport_clk_cross ( - input wire rst, // Can be either clock domain, but must be glitch-free - - //--------------------------------------------------------------------------- - // Input Clock Domain (Slave Interface) - //--------------------------------------------------------------------------- - - input wire s_ctrlport_clk, - input wire s_ctrlport_req_wr, - input wire s_ctrlport_req_rd, - input wire [19:0] s_ctrlport_req_addr, - input wire [ 9:0] s_ctrlport_req_portid, - input wire [15:0] s_ctrlport_req_rem_epid, - input wire [ 9:0] s_ctrlport_req_rem_portid, - input wire [31:0] s_ctrlport_req_data, - input wire [ 3:0] s_ctrlport_req_byte_en, - input wire s_ctrlport_req_has_time, - input wire [63:0] s_ctrlport_req_time, - output wire s_ctrlport_resp_ack, - output wire [ 1:0] s_ctrlport_resp_status, - output wire [31:0] s_ctrlport_resp_data, - - //--------------------------------------------------------------------------- - // Output Clock Domain (Master Interface) - //--------------------------------------------------------------------------- - - input wire m_ctrlport_clk, - output wire m_ctrlport_req_wr, - output wire m_ctrlport_req_rd, - output wire [19:0] m_ctrlport_req_addr, - output wire [ 9:0] m_ctrlport_req_portid, - output wire [15:0] m_ctrlport_req_rem_epid, - output wire [ 9:0] m_ctrlport_req_rem_portid, - output wire [31:0] m_ctrlport_req_data, - output wire [ 3:0] m_ctrlport_req_byte_en, - output wire m_ctrlport_req_has_time, - output wire [63:0] m_ctrlport_req_time, - input wire m_ctrlport_resp_ack, - input wire [ 1:0] m_ctrlport_resp_status, - input wire [31:0] m_ctrlport_resp_data -); - //--------------------------------------------------------------------------- - // Reset sync to both clock domains - //--------------------------------------------------------------------------- - wire m_rst, s_rst; - reset_sync master_reset_sync_inst ( - .clk(m_ctrlport_clk), .reset_in(rst), .reset_out(m_rst) - ); - reset_sync slave_reset_sync_inst ( - .clk(s_ctrlport_clk), .reset_in(rst), .reset_out(s_rst) - ); - - //--------------------------------------------------------------------------- - // Slave to Master Clock Crossing (Request) - //--------------------------------------------------------------------------- - - localparam REQ_W = - 1 + // ctrlport_req_wr - 1 + // ctrlport_req_rd - 20 + // ctrlport_req_addr - 10 + // ctrlport_req_portid - 16 + // ctrlport_req_rem_epid - 10 + // ctrlport_req_rem_portid - 32 + // ctrlport_req_data - 4 + // ctrlport_req_byte_en - 1 + // ctrlport_req_has_time - 64; // ctrlport_req_time - - wire [ REQ_W-1:0] s_req_flat; - wire [ REQ_W-1:0] m_req_flat; - wire m_req_flat_valid; - wire m_ctrlport_req_wr_tmp; - wire m_ctrlport_req_rd_tmp; - - assign s_req_flat = { - s_ctrlport_req_wr, - s_ctrlport_req_rd, - s_ctrlport_req_addr, - s_ctrlport_req_portid, - s_ctrlport_req_rem_epid, - s_ctrlport_req_rem_portid, - s_ctrlport_req_data, - s_ctrlport_req_byte_en, - s_ctrlport_req_has_time, - s_ctrlport_req_time - }; - - // Busy flag can be ignored as the response handshake takes at least the same - // amount of cycles to transfer the response as this handshake instance needs - // to release the busy flag as they are configured with the same amount of - // synchronization stages. Furthermore the ctrlport protocol just allows for - // one transaction to be active at the same time. A request can only be issued - // once the response is provided. - handshake #( - .WIDTH(REQ_W) - ) req_handshake_inst ( - .clk_a(s_ctrlport_clk), - .rst_a(s_rst), - .valid_a((s_ctrlport_req_wr | s_ctrlport_req_rd) & ~s_rst), - .data_a(s_req_flat), - .busy_a(), - .clk_b(m_ctrlport_clk), - .valid_b(m_req_flat_valid), - .data_b(m_req_flat) - ); - - assign { - m_ctrlport_req_wr_tmp, - m_ctrlport_req_rd_tmp, - m_ctrlport_req_addr, - m_ctrlport_req_portid, - m_ctrlport_req_rem_epid, - m_ctrlport_req_rem_portid, - m_ctrlport_req_data, - m_ctrlport_req_byte_en, - m_ctrlport_req_has_time, - m_ctrlport_req_time - } = m_req_flat; - - assign m_ctrlport_req_wr = m_ctrlport_req_wr_tmp & m_req_flat_valid & ~m_rst; - assign m_ctrlport_req_rd = m_ctrlport_req_rd_tmp & m_req_flat_valid & ~m_rst; - - - //--------------------------------------------------------------------------- - // Master to Slave Clock Crossing (Response) - //--------------------------------------------------------------------------- - - localparam RESP_W = - 1 + // ctrlport_resp_ack, - 2 + // ctrlport_resp_status, - 32; // ctrlport_resp_data - - wire [RESP_W-1:0] m_resp_flat; - wire [RESP_W-1:0] s_resp_flat; - wire s_resp_flat_valid; - wire s_ctrlport_resp_ack_tmp; - - assign m_resp_flat = { - m_ctrlport_resp_ack, - m_ctrlport_resp_status, - m_ctrlport_resp_data - }; - - // Busy flag can be ignored as the request handshake takes at least the same - // amount of cycles to transfer the request as this handshake instance needs - // to release the busy flag as they are configured with the same amount of - // synchronization stages. Furthermore the ctrlport protocol just allows for - // one transaction to be active at the same time. A response can only be - // issued once the request is available. - handshake #( - .WIDTH(RESP_W) - ) resp_handshake_inst ( - .clk_a(m_ctrlport_clk), - .rst_a(m_rst), - .valid_a(m_ctrlport_resp_ack & ~m_rst), - .data_a(m_resp_flat), - .busy_a(), - .clk_b(s_ctrlport_clk), - .valid_b(s_resp_flat_valid), - .data_b(s_resp_flat) - ); - - assign { - s_ctrlport_resp_ack_tmp, - s_ctrlport_resp_status, - s_ctrlport_resp_data - } = s_resp_flat; - - assign s_ctrlport_resp_ack = s_ctrlport_resp_ack_tmp & s_resp_flat_valid & ~s_rst; - -endmodule diff --git a/lib/rfnoc/utils/ctrlport_combiner.sv b/lib/rfnoc/utils/ctrlport_combiner.sv new file mode 100644 index 0000000..6717f28 --- /dev/null +++ b/lib/rfnoc/utils/ctrlport_combiner.sv @@ -0,0 +1,125 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: ctrlport_combiner +// +// Description: +// +// This block is an arbiter that merges control-port interfaces. This block is +// used when you have multiple control-port masters that need to access a +// single slave. For example, a NoC block with multiple submodules that each +// need to read and/or write registers outside of themselves. +// +// This module combines the control-port requests from multiple masters into a +// single request for one slave. Simultaneous requests are handled in the order +// specified by PRIORITY. The responding ACK is routed back to the requester. +// +// The module has been designed so that the latency through it is always the +// same when PRIORITY=1 and there is no contention, so that it can be used in +// applications where deterministic behavior is desired. +// +// Parameters: +// +// NUM_MASTERS : The number of control-port masters to connect to a single +// control-port slave. +// PRIORITY : Use PRIORITY = 0 for round robin arbitration, PRIORITY = 1 +// for priority arbitration (lowest number port serviced first). +// + + +module ctrlport_combiner + import ctrlport_pkg::*; +#( + int NUM_MASTERS = 2, + bit PRIORITY = 0 +) ( + input logic ctrlport_clk, + input logic ctrlport_rst, + + // Requests from multiple masters + input logic [ NUM_MASTERS-1:0] s_ctrlport_req_wr, + input logic [ NUM_MASTERS-1:0] s_ctrlport_req_rd, + input logic [ CTRLPORT_ADDR_W*NUM_MASTERS-1:0] s_ctrlport_req_addr, + input logic [ CTRLPORT_PORTID_W*NUM_MASTERS-1:0] s_ctrlport_req_portid, + input logic [CTRLPORT_REM_EPID_W*NUM_MASTERS-1:0] s_ctrlport_req_rem_epid, + input logic [ CTRLPORT_PORTID_W*NUM_MASTERS-1:0] s_ctrlport_req_rem_portid, + input logic [ CTRLPORT_DATA_W*NUM_MASTERS-1:0] s_ctrlport_req_data, + input logic [ CTRLPORT_BYTE_EN_W*NUM_MASTERS-1:0] s_ctrlport_req_byte_en, + input logic [ NUM_MASTERS-1:0] s_ctrlport_req_has_time, + input logic [ CTRLPORT_TIME_W*NUM_MASTERS-1:0] s_ctrlport_req_time, + // Responses to multiple masters + output logic [ NUM_MASTERS-1:0] s_ctrlport_resp_ack, + output logic [ CTRLPORT_STS_W*NUM_MASTERS-1:0] s_ctrlport_resp_status, + output logic [ CTRLPORT_DATA_W*NUM_MASTERS-1:0] s_ctrlport_resp_data, + + // Request to a single slave + output logic m_ctrlport_req_wr, + output logic m_ctrlport_req_rd, + output logic [ CTRLPORT_ADDR_W-1:0] m_ctrlport_req_addr, + output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_portid, + output logic [CTRLPORT_REM_EPID_W-1:0] m_ctrlport_req_rem_epid, + output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_rem_portid, + output logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_req_data, + output logic [ CTRLPORT_BYTE_EN_W-1:0] m_ctrlport_req_byte_en, + output logic m_ctrlport_req_has_time, + output logic [ CTRLPORT_TIME_W-1:0] m_ctrlport_req_time, + // Response from a single slave + input logic m_ctrlport_resp_ack, + input logic [ CTRLPORT_STS_W-1:0] m_ctrlport_resp_status, + input logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_resp_data +); + + // Define interfaces + ctrlport_if slave_ctrlport[NUM_MASTERS](.clk(ctrlport_clk), .rst(ctrlport_rst)); + ctrlport_if master_ctrlport(.clk(ctrlport_clk), .rst(ctrlport_rst)); + + // Map existing ports to ctrlport_if + for (genvar i=0; i= START_ADDRESS) && (s_ctrlport_req_addr <= LAST_ADDRESS)) begin - s_ctrlport_resp_ack <= s_ctrlport_req_wr | s_ctrlport_req_rd; - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end -end - -// other outputs are fixed -assign s_ctrlport_resp_status = CTRL_STS_CMDERR; -assign s_ctrlport_resp_data = { CTRLPORT_DATA_W {1'b0}}; - -endmodule \ No newline at end of file diff --git a/lib/rfnoc/utils/ctrlport_window.sv b/lib/rfnoc/utils/ctrlport_window.sv new file mode 100644 index 0000000..8972b4c --- /dev/null +++ b/lib/rfnoc/utils/ctrlport_window.sv @@ -0,0 +1,109 @@ +// +// Copyright 2025 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: ctrlport_window +// +// Description: +// +// Copy requests from slave to master interface when s_ctrlport_req_addr is in +// address range specified by BASE_ADDRESS and WINDOW_SIZE. The modules does +// not use any registers and therefore does not need ctrlport_clk and +// ctrlport_rst. +// +// Parameters: +// +// BASE_ADDRESS: Base address of the memory window. +// WINDOW_SIZE: Size of the memory window. +// + +module ctrlport_window + import ctrlport_pkg::*; +#( + int BASE_ADDRESS = 0, + int WINDOW_SIZE = 32 +) ( + // Slave Interface + input logic s_ctrlport_req_wr, + input logic s_ctrlport_req_rd, + input logic [ CTRLPORT_ADDR_W-1:0] s_ctrlport_req_addr, + input logic [ CTRLPORT_PORTID_W-1:0] s_ctrlport_req_portid, + input logic [CTRLPORT_REM_EPID_W-1:0] s_ctrlport_req_rem_epid, + input logic [ CTRLPORT_PORTID_W-1:0] s_ctrlport_req_rem_portid, + input logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_req_data, + input logic [ CTRLPORT_BYTE_EN_W-1:0] s_ctrlport_req_byte_en, + input logic s_ctrlport_req_has_time, + input logic [ CTRLPORT_TIME_W-1:0] s_ctrlport_req_time, + output logic s_ctrlport_resp_ack, + output logic [ CTRLPORT_STS_W-1:0] s_ctrlport_resp_status, + output logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_resp_data, + + // Master Interface + output logic m_ctrlport_req_wr, + output logic m_ctrlport_req_rd, + output logic [ CTRLPORT_ADDR_W-1:0] m_ctrlport_req_addr, + output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_portid, + output logic [CTRLPORT_REM_EPID_W-1:0] m_ctrlport_req_rem_epid, + output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_rem_portid, + output logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_req_data, + output logic [ CTRLPORT_BYTE_EN_W-1:0] m_ctrlport_req_byte_en, + output logic m_ctrlport_req_has_time, + output logic [ CTRLPORT_TIME_W-1:0] m_ctrlport_req_time, + input logic m_ctrlport_resp_ack, + input logic [ CTRLPORT_STS_W-1:0] m_ctrlport_resp_status, + input logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_resp_data +); + + // Define interfaces + logic dummy_clk = '0; + logic dummy_rst = '0; + ctrlport_if s_ctrlport_if(.clk(dummy_clk), .rst(dummy_rst)); + ctrlport_if m_ctrlport_if(.clk(dummy_clk), .rst(dummy_rst));; + + // Map existing ports to ctrlport_if + always_comb begin + s_ctrlport_if.req.wr = s_ctrlport_req_wr; + s_ctrlport_if.req.rd = s_ctrlport_req_rd; + s_ctrlport_if.req.addr = s_ctrlport_req_addr; + s_ctrlport_if.req.port_id = s_ctrlport_req_portid; + s_ctrlport_if.req.remote_epid = s_ctrlport_req_rem_epid; + s_ctrlport_if.req.remote_portid = s_ctrlport_req_rem_portid; + s_ctrlport_if.req.data = s_ctrlport_req_data; + s_ctrlport_if.req.byte_en = s_ctrlport_req_byte_en; + s_ctrlport_if.req.has_time = s_ctrlport_req_has_time; + s_ctrlport_if.req.timestamp = s_ctrlport_req_time; + + s_ctrlport_resp_ack = s_ctrlport_if.resp.ack; + s_ctrlport_resp_status = s_ctrlport_if.resp.status; + s_ctrlport_resp_data = s_ctrlport_if.resp.data; + end + + // Instantiate ctrlport_if_clk_cross module + ctrlport_if_window #( + .BASE_ADDRESS(BASE_ADDRESS), + .WINDOW_SIZE(WINDOW_SIZE) + ) window_inst ( + .s_ctrlport(s_ctrlport_if), + .m_ctrlport(m_ctrlport_if) + ); + + // Unpack ctrlport_if to output port + always_comb begin + m_ctrlport_req_wr = m_ctrlport_if.req.wr; + m_ctrlport_req_rd = m_ctrlport_if.req.rd; + m_ctrlport_req_addr = m_ctrlport_if.req.addr; + m_ctrlport_req_portid = m_ctrlport_if.req.port_id; + m_ctrlport_req_rem_epid = m_ctrlport_if.req.remote_epid; + m_ctrlport_req_rem_portid = m_ctrlport_if.req.remote_portid; + m_ctrlport_req_data = m_ctrlport_if.req.data; + m_ctrlport_req_byte_en = m_ctrlport_if.req.byte_en; + m_ctrlport_req_has_time = m_ctrlport_if.req.has_time; + m_ctrlport_req_time = m_ctrlport_if.req.timestamp; + + m_ctrlport_if.resp.ack = m_ctrlport_resp_ack; + m_ctrlport_if.resp.status = ctrlport_status_t'(m_ctrlport_resp_status); + m_ctrlport_if.resp.data = m_ctrlport_resp_data; + end + +endmodule diff --git a/lib/rfnoc/utils/ctrlport_window.v b/lib/rfnoc/utils/ctrlport_window.v deleted file mode 100644 index 4a886d3..0000000 --- a/lib/rfnoc/utils/ctrlport_window.v +++ /dev/null @@ -1,73 +0,0 @@ -// -// Copyright 2021 Ettus Research, a National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: ctrlport_window -// -// Description: -// Copy requests from slave to master interface when s_ctrlport_req_addr is in -// address range specified by BASE_ADDRESS and WINDOW_SIZE. The modules does -// not use any registers and therefore does not need ctrlport_clk and -// ctrlport_rst. -// - -`default_nettype none - -module ctrlport_window #( - parameter BASE_ADDRESS = 0, - parameter WINDOW_SIZE = 32 -) ( - // Slave Interface - input wire s_ctrlport_req_wr, - input wire s_ctrlport_req_rd, - input wire [19:0] s_ctrlport_req_addr, - input wire [ 9:0] s_ctrlport_req_portid, - input wire [15:0] s_ctrlport_req_rem_epid, - input wire [ 9:0] s_ctrlport_req_rem_portid, - input wire [31:0] s_ctrlport_req_data, - input wire [ 3:0] s_ctrlport_req_byte_en, - input wire s_ctrlport_req_has_time, - input wire [63:0] s_ctrlport_req_time, - output wire s_ctrlport_resp_ack, - output wire [ 1:0] s_ctrlport_resp_status, - output wire [31:0] s_ctrlport_resp_data, - - // Master Interface - output wire m_ctrlport_req_wr, - output wire m_ctrlport_req_rd, - output wire [19:0] m_ctrlport_req_addr, - output wire [ 9:0] m_ctrlport_req_portid, - output wire [15:0] m_ctrlport_req_rem_epid, - output wire [ 9:0] m_ctrlport_req_rem_portid, - output wire [31:0] m_ctrlport_req_data, - output wire [ 3:0] m_ctrlport_req_byte_en, - output wire m_ctrlport_req_has_time, - output wire [63:0] m_ctrlport_req_time, - input wire m_ctrlport_resp_ack, - input wire [ 1:0] m_ctrlport_resp_status, - input wire [31:0] m_ctrlport_resp_data -); - - // Mask write and read flag - wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + WINDOW_SIZE); - assign m_ctrlport_req_wr = s_ctrlport_req_wr & address_in_range; - assign m_ctrlport_req_rd = s_ctrlport_req_rd & address_in_range; - - // Forward all other signals untouched. - assign m_ctrlport_req_addr = s_ctrlport_req_addr; - assign m_ctrlport_req_portid = s_ctrlport_req_portid; - assign m_ctrlport_req_rem_epid = s_ctrlport_req_rem_epid; - assign m_ctrlport_req_rem_portid = s_ctrlport_req_rem_portid; - assign m_ctrlport_req_data = s_ctrlport_req_data; - assign m_ctrlport_req_byte_en = s_ctrlport_req_byte_en; - assign m_ctrlport_req_has_time = s_ctrlport_req_has_time; - assign m_ctrlport_req_time = s_ctrlport_req_time; - - assign s_ctrlport_resp_ack = m_ctrlport_resp_ack; - assign s_ctrlport_resp_status = m_ctrlport_resp_status; - assign s_ctrlport_resp_data = m_ctrlport_resp_data; - -endmodule - -`default_nettype wire