fpga: lib: redirect old ctrlport modules to interface based ones
Original-commit: bf294111b9f49efb6373908274bc8d31bb8cb11d
This commit is contained in:
Max Köhler
@@ -17,19 +17,19 @@ context_handler_sync.v \
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context_builder.v \
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context_parser.v \
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ctrlport_timer.v \
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ctrlport_combiner.v \
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ctrlport_decoder.v \
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ctrlport_decoder_param.v \
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ctrlport_window.v \
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ctrlport_splitter.v \
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ctrlport_combiner.sv \
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ctrlport_decoder.sv \
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ctrlport_decoder_param.sv \
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ctrlport_window.sv \
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ctrlport_splitter.sv \
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ctrlport_resp_combine.v \
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ctrlport_clk_cross.v \
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ctrlport_clk_cross.sv \
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ctrlport_reg_rw.v \
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ctrlport_reg_ro.v \
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ctrlport_to_settings_bus.v \
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noc_shell_generic_ctrlport_pyld_chdr.v \
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timekeeper.v \
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ctrlport_terminator.v \
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ctrlport_terminator.sv \
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chdr_strip_header.sv \
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ctrlport_if_clk_cross.sv \
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ctrlport_if_combiner.sv \
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@@ -0,0 +1,115 @@
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//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_clk_cross
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//
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// Description:
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//
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// Crosses a CTRL Port request and response between two clock domains.
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//
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module ctrlport_clk_cross
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import ctrlport_pkg::*;
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(
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input logic rst, // Can be either clock domain, but must be glitch-free
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//---------------------------------------------------------------------------
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// Input Clock Domain (Slave Interface)
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//---------------------------------------------------------------------------
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input logic s_ctrlport_clk,
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input logic s_ctrlport_req_wr,
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input logic s_ctrlport_req_rd,
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input logic [ CTRLPORT_ADDR_W-1:0] s_ctrlport_req_addr,
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input logic [ CTRLPORT_PORTID_W-1:0] s_ctrlport_req_portid,
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input logic [CTRLPORT_REM_EPID_W-1:0] s_ctrlport_req_rem_epid,
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input logic [ CTRLPORT_PORTID_W-1:0] s_ctrlport_req_rem_portid,
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input logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_req_data,
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input logic [ CTRLPORT_BYTE_EN_W-1:0] s_ctrlport_req_byte_en,
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input logic s_ctrlport_req_has_time,
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input logic [ CTRLPORT_TIME_W-1:0] s_ctrlport_req_time,
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output logic s_ctrlport_resp_ack,
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output logic [ CTRLPORT_STS_W-1:0] s_ctrlport_resp_status,
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output logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_resp_data,
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//---------------------------------------------------------------------------
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// Output Clock Domain (Master Interface)
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//---------------------------------------------------------------------------
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input logic m_ctrlport_clk,
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output logic m_ctrlport_req_wr,
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output logic m_ctrlport_req_rd,
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output logic [ CTRLPORT_ADDR_W-1:0] m_ctrlport_req_addr,
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output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_portid,
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output logic [CTRLPORT_REM_EPID_W-1:0] m_ctrlport_req_rem_epid,
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output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_rem_portid,
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output logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_req_data,
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output logic [ CTRLPORT_BYTE_EN_W-1:0] m_ctrlport_req_byte_en,
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output logic m_ctrlport_req_has_time,
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output logic [ CTRLPORT_TIME_W-1:0] m_ctrlport_req_time,
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input logic m_ctrlport_resp_ack,
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input logic [ CTRLPORT_STS_W-1:0] m_ctrlport_resp_status,
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input logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_resp_data
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);
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import ctrlport_pkg::*;
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// Reset sync to both clock domains
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logic m_rst, s_rst;
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reset_sync slave_reset_sync_inst (
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.clk(s_ctrlport_clk), .reset_in(rst), .reset_out(s_rst)
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);
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reset_sync master_reset_sync_inst (
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.clk(m_ctrlport_clk), .reset_in(rst), .reset_out(m_rst)
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);
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// Define interfaces
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ctrlport_if s_ctrlport_if(.clk(s_ctrlport_clk), .rst(s_rst));
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ctrlport_if m_ctrlport_if(.clk(m_ctrlport_clk), .rst(m_rst));
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// Map existing ports to ctrlport_if
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always_comb begin
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s_ctrlport_if.req.wr = s_ctrlport_req_wr;
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s_ctrlport_if.req.rd = s_ctrlport_req_rd;
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s_ctrlport_if.req.addr = s_ctrlport_req_addr;
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s_ctrlport_if.req.port_id = s_ctrlport_req_portid;
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s_ctrlport_if.req.remote_epid = s_ctrlport_req_rem_epid;
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s_ctrlport_if.req.remote_portid = s_ctrlport_req_rem_portid;
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s_ctrlport_if.req.data = s_ctrlport_req_data;
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s_ctrlport_if.req.byte_en = s_ctrlport_req_byte_en;
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s_ctrlport_if.req.has_time = s_ctrlport_req_has_time;
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s_ctrlport_if.req.timestamp = s_ctrlport_req_time;
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s_ctrlport_resp_ack = s_ctrlport_if.resp.ack;
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s_ctrlport_resp_status = s_ctrlport_if.resp.status;
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s_ctrlport_resp_data = s_ctrlport_if.resp.data;
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end
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// Instantiate ctrlport_if_clk_cross module
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ctrlport_if_clk_cross clk_cross_inst (
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.s_ctrlport(s_ctrlport_if),
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.m_ctrlport(m_ctrlport_if)
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);
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// Unpack ctrlport_if to output port
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always_comb begin
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m_ctrlport_req_wr = m_ctrlport_if.req.wr;
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m_ctrlport_req_rd = m_ctrlport_if.req.rd;
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m_ctrlport_req_addr = m_ctrlport_if.req.addr;
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m_ctrlport_req_portid = m_ctrlport_if.req.port_id;
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m_ctrlport_req_rem_epid = m_ctrlport_if.req.remote_epid;
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m_ctrlport_req_rem_portid = m_ctrlport_if.req.remote_portid;
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m_ctrlport_req_data = m_ctrlport_if.req.data;
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m_ctrlport_req_byte_en = m_ctrlport_if.req.byte_en;
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m_ctrlport_req_has_time = m_ctrlport_if.req.has_time;
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m_ctrlport_req_time = m_ctrlport_if.req.timestamp;
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m_ctrlport_if.resp.ack = m_ctrlport_resp_ack;
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m_ctrlport_if.resp.status = ctrlport_status_t'(m_ctrlport_resp_status);
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m_ctrlport_if.resp.data = m_ctrlport_resp_data;
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end
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endmodule
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@@ -1,184 +0,0 @@
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//
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// Copyright 2019 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_clk_cross
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//
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// Description:
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//
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// Crosses a CTRL Port request and response between two clock domains.
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//
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module ctrlport_clk_cross (
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input wire rst, // Can be either clock domain, but must be glitch-free
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//---------------------------------------------------------------------------
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// Input Clock Domain (Slave Interface)
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//---------------------------------------------------------------------------
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input wire s_ctrlport_clk,
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [ 9:0] s_ctrlport_req_portid,
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input wire [15:0] s_ctrlport_req_rem_epid,
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input wire [ 9:0] s_ctrlport_req_rem_portid,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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//---------------------------------------------------------------------------
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// Output Clock Domain (Master Interface)
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//---------------------------------------------------------------------------
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input wire m_ctrlport_clk,
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output wire m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [ 9:0] m_ctrlport_req_portid,
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output wire [15:0] m_ctrlport_req_rem_epid,
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output wire [ 9:0] m_ctrlport_req_rem_portid,
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output wire [31:0] m_ctrlport_req_data,
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output wire [ 3:0] m_ctrlport_req_byte_en,
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output wire m_ctrlport_req_has_time,
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output wire [63:0] m_ctrlport_req_time,
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data
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);
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//---------------------------------------------------------------------------
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// Reset sync to both clock domains
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//---------------------------------------------------------------------------
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wire m_rst, s_rst;
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reset_sync master_reset_sync_inst (
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.clk(m_ctrlport_clk), .reset_in(rst), .reset_out(m_rst)
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);
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reset_sync slave_reset_sync_inst (
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.clk(s_ctrlport_clk), .reset_in(rst), .reset_out(s_rst)
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);
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//---------------------------------------------------------------------------
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// Slave to Master Clock Crossing (Request)
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//---------------------------------------------------------------------------
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localparam REQ_W =
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1 + // ctrlport_req_wr
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1 + // ctrlport_req_rd
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20 + // ctrlport_req_addr
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10 + // ctrlport_req_portid
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16 + // ctrlport_req_rem_epid
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10 + // ctrlport_req_rem_portid
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32 + // ctrlport_req_data
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4 + // ctrlport_req_byte_en
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1 + // ctrlport_req_has_time
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64; // ctrlport_req_time
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wire [ REQ_W-1:0] s_req_flat;
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wire [ REQ_W-1:0] m_req_flat;
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wire m_req_flat_valid;
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wire m_ctrlport_req_wr_tmp;
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wire m_ctrlport_req_rd_tmp;
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assign s_req_flat = {
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s_ctrlport_req_wr,
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s_ctrlport_req_rd,
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s_ctrlport_req_addr,
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s_ctrlport_req_portid,
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s_ctrlport_req_rem_epid,
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s_ctrlport_req_rem_portid,
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s_ctrlport_req_data,
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s_ctrlport_req_byte_en,
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s_ctrlport_req_has_time,
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s_ctrlport_req_time
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};
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// Busy flag can be ignored as the response handshake takes at least the same
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// amount of cycles to transfer the response as this handshake instance needs
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// to release the busy flag as they are configured with the same amount of
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// synchronization stages. Furthermore the ctrlport protocol just allows for
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// one transaction to be active at the same time. A request can only be issued
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// once the response is provided.
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handshake #(
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.WIDTH(REQ_W)
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) req_handshake_inst (
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.clk_a(s_ctrlport_clk),
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.rst_a(s_rst),
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.valid_a((s_ctrlport_req_wr | s_ctrlport_req_rd) & ~s_rst),
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.data_a(s_req_flat),
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.busy_a(),
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.clk_b(m_ctrlport_clk),
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.valid_b(m_req_flat_valid),
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.data_b(m_req_flat)
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);
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assign {
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m_ctrlport_req_wr_tmp,
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m_ctrlport_req_rd_tmp,
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m_ctrlport_req_addr,
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m_ctrlport_req_portid,
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m_ctrlport_req_rem_epid,
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m_ctrlport_req_rem_portid,
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m_ctrlport_req_data,
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m_ctrlport_req_byte_en,
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m_ctrlport_req_has_time,
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m_ctrlport_req_time
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} = m_req_flat;
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assign m_ctrlport_req_wr = m_ctrlport_req_wr_tmp & m_req_flat_valid & ~m_rst;
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assign m_ctrlport_req_rd = m_ctrlport_req_rd_tmp & m_req_flat_valid & ~m_rst;
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//---------------------------------------------------------------------------
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// Master to Slave Clock Crossing (Response)
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//---------------------------------------------------------------------------
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localparam RESP_W =
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1 + // ctrlport_resp_ack,
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2 + // ctrlport_resp_status,
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32; // ctrlport_resp_data
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wire [RESP_W-1:0] m_resp_flat;
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wire [RESP_W-1:0] s_resp_flat;
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wire s_resp_flat_valid;
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wire s_ctrlport_resp_ack_tmp;
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assign m_resp_flat = {
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m_ctrlport_resp_ack,
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m_ctrlport_resp_status,
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m_ctrlport_resp_data
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};
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// Busy flag can be ignored as the request handshake takes at least the same
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// amount of cycles to transfer the request as this handshake instance needs
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// to release the busy flag as they are configured with the same amount of
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// synchronization stages. Furthermore the ctrlport protocol just allows for
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// one transaction to be active at the same time. A response can only be
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// issued once the request is available.
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handshake #(
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.WIDTH(RESP_W)
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) resp_handshake_inst (
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.clk_a(m_ctrlport_clk),
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.rst_a(m_rst),
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.valid_a(m_ctrlport_resp_ack & ~m_rst),
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.data_a(m_resp_flat),
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.busy_a(),
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.clk_b(s_ctrlport_clk),
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.valid_b(s_resp_flat_valid),
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.data_b(s_resp_flat)
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);
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assign {
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s_ctrlport_resp_ack_tmp,
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s_ctrlport_resp_status,
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s_ctrlport_resp_data
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} = s_resp_flat;
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assign s_ctrlport_resp_ack = s_ctrlport_resp_ack_tmp & s_resp_flat_valid & ~s_rst;
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endmodule
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@@ -0,0 +1,125 @@
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//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_combiner
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//
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// Description:
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//
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// This block is an arbiter that merges control-port interfaces. This block is
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// used when you have multiple control-port masters that need to access a
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// single slave. For example, a NoC block with multiple submodules that each
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// need to read and/or write registers outside of themselves.
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//
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// This module combines the control-port requests from multiple masters into a
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// single request for one slave. Simultaneous requests are handled in the order
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// specified by PRIORITY. The responding ACK is routed back to the requester.
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//
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// The module has been designed so that the latency through it is always the
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// same when PRIORITY=1 and there is no contention, so that it can be used in
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// applications where deterministic behavior is desired.
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//
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// Parameters:
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//
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// NUM_MASTERS : The number of control-port masters to connect to a single
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// control-port slave.
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// PRIORITY : Use PRIORITY = 0 for round robin arbitration, PRIORITY = 1
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// for priority arbitration (lowest number port serviced first).
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//
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module ctrlport_combiner
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import ctrlport_pkg::*;
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#(
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int NUM_MASTERS = 2,
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bit PRIORITY = 0
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) (
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input logic ctrlport_clk,
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input logic ctrlport_rst,
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// Requests from multiple masters
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input logic [ NUM_MASTERS-1:0] s_ctrlport_req_wr,
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input logic [ NUM_MASTERS-1:0] s_ctrlport_req_rd,
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input logic [ CTRLPORT_ADDR_W*NUM_MASTERS-1:0] s_ctrlport_req_addr,
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input logic [ CTRLPORT_PORTID_W*NUM_MASTERS-1:0] s_ctrlport_req_portid,
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input logic [CTRLPORT_REM_EPID_W*NUM_MASTERS-1:0] s_ctrlport_req_rem_epid,
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input logic [ CTRLPORT_PORTID_W*NUM_MASTERS-1:0] s_ctrlport_req_rem_portid,
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input logic [ CTRLPORT_DATA_W*NUM_MASTERS-1:0] s_ctrlport_req_data,
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input logic [ CTRLPORT_BYTE_EN_W*NUM_MASTERS-1:0] s_ctrlport_req_byte_en,
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input logic [ NUM_MASTERS-1:0] s_ctrlport_req_has_time,
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input logic [ CTRLPORT_TIME_W*NUM_MASTERS-1:0] s_ctrlport_req_time,
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// Responses to multiple masters
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output logic [ NUM_MASTERS-1:0] s_ctrlport_resp_ack,
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output logic [ CTRLPORT_STS_W*NUM_MASTERS-1:0] s_ctrlport_resp_status,
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output logic [ CTRLPORT_DATA_W*NUM_MASTERS-1:0] s_ctrlport_resp_data,
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// Request to a single slave
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output logic m_ctrlport_req_wr,
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output logic m_ctrlport_req_rd,
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output logic [ CTRLPORT_ADDR_W-1:0] m_ctrlport_req_addr,
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output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_portid,
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output logic [CTRLPORT_REM_EPID_W-1:0] m_ctrlport_req_rem_epid,
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output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_rem_portid,
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output logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_req_data,
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output logic [ CTRLPORT_BYTE_EN_W-1:0] m_ctrlport_req_byte_en,
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output logic m_ctrlport_req_has_time,
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output logic [ CTRLPORT_TIME_W-1:0] m_ctrlport_req_time,
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// Response from a single slave
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input logic m_ctrlport_resp_ack,
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input logic [ CTRLPORT_STS_W-1:0] m_ctrlport_resp_status,
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input logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_resp_data
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);
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// Define interfaces
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ctrlport_if slave_ctrlport[NUM_MASTERS](.clk(ctrlport_clk), .rst(ctrlport_rst));
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ctrlport_if master_ctrlport(.clk(ctrlport_clk), .rst(ctrlport_rst));
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// Map existing ports to ctrlport_if
|
||||
for (genvar i=0; i<NUM_MASTERS; i++) begin : input_gen
|
||||
always_comb begin
|
||||
slave_ctrlport[i].req.wr = s_ctrlport_req_wr[i];
|
||||
slave_ctrlport[i].req.rd = s_ctrlport_req_rd[i];
|
||||
slave_ctrlport[i].req.addr = s_ctrlport_req_addr[CTRLPORT_ADDR_W*i +: CTRLPORT_ADDR_W];
|
||||
slave_ctrlport[i].req.port_id = s_ctrlport_req_portid[CTRLPORT_PORTID_W*i +: CTRLPORT_PORTID_W];
|
||||
slave_ctrlport[i].req.remote_epid = s_ctrlport_req_rem_epid[CTRLPORT_REM_EPID_W*i +: CTRLPORT_REM_EPID_W];
|
||||
slave_ctrlport[i].req.remote_portid = s_ctrlport_req_rem_portid[CTRLPORT_PORTID_W*i +: CTRLPORT_PORTID_W];
|
||||
slave_ctrlport[i].req.data = s_ctrlport_req_data[CTRLPORT_DATA_W*i +: CTRLPORT_DATA_W];
|
||||
slave_ctrlport[i].req.byte_en = s_ctrlport_req_byte_en[CTRLPORT_BYTE_EN_W*i +: CTRLPORT_BYTE_EN_W];
|
||||
slave_ctrlport[i].req.has_time = s_ctrlport_req_has_time[i];
|
||||
slave_ctrlport[i].req.timestamp = s_ctrlport_req_time[CTRLPORT_TIME_W*i +: CTRLPORT_TIME_W];
|
||||
|
||||
s_ctrlport_resp_ack[i] = slave_ctrlport[i].resp.ack;
|
||||
s_ctrlport_resp_status[CTRLPORT_STS_W*i +: CTRLPORT_STS_W] = slave_ctrlport[i].resp.status;
|
||||
s_ctrlport_resp_data[CTRLPORT_DATA_W*i +: CTRLPORT_DATA_W] = slave_ctrlport[i].resp.data;
|
||||
end
|
||||
end
|
||||
|
||||
// Instantiate ctrlport_if_combiner module
|
||||
ctrlport_if_combiner #(
|
||||
.NUM_MASTERS(NUM_MASTERS),
|
||||
.PRIORITY(PRIORITY)
|
||||
) ctrlport_if_combiner_inst (
|
||||
.s_ctrlport(slave_ctrlport),
|
||||
.m_ctrlport(master_ctrlport)
|
||||
);
|
||||
|
||||
// Unpack ctrlport_if to output port
|
||||
always_comb begin
|
||||
m_ctrlport_req_wr = master_ctrlport.req.wr;
|
||||
m_ctrlport_req_rd = master_ctrlport.req.rd;
|
||||
m_ctrlport_req_addr = master_ctrlport.req.addr;
|
||||
m_ctrlport_req_portid = master_ctrlport.req.port_id;
|
||||
m_ctrlport_req_rem_epid = master_ctrlport.req.remote_epid;
|
||||
m_ctrlport_req_rem_portid = master_ctrlport.req.remote_portid;
|
||||
m_ctrlport_req_data = master_ctrlport.req.data;
|
||||
m_ctrlport_req_byte_en = master_ctrlport.req.byte_en;
|
||||
m_ctrlport_req_has_time = master_ctrlport.req.has_time;
|
||||
m_ctrlport_req_time = master_ctrlport.req.timestamp;
|
||||
|
||||
master_ctrlport.resp.ack = m_ctrlport_resp_ack;
|
||||
master_ctrlport.resp.status = ctrlport_status_t'(m_ctrlport_resp_status);
|
||||
master_ctrlport.resp.data = m_ctrlport_resp_data;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,270 +0,0 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_combiner
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This block is an arbiter that merges control-port interfaces. This block is
|
||||
// used when you have multiple control-port masters that need to access a
|
||||
// single slave. For example, a NoC block with multiple submodules that each
|
||||
// need to read and/or write registers outside of themselves.
|
||||
//
|
||||
// This module combines the control-port requests from multiple masters into a
|
||||
// single request for one slave. Simultaneous requests are handled in the order
|
||||
// specified by PRIORITY. The responding ACK is routed back to the requester.
|
||||
//
|
||||
// The module has been designed so that the latency through it is always the
|
||||
// same when PRIORITY=1 and there is no contention, so that it can be used in
|
||||
// applications where deterministic behavior is desired.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// NUM_MASTERS : The number of control-port masters to connect to a single
|
||||
// control-port slave.
|
||||
// PRIORITY : Use PRIORITY = 0 for round robin arbitration, PRIORITY = 1
|
||||
// for priority arbitration (lowest number port serviced first).
|
||||
//
|
||||
|
||||
|
||||
module ctrlport_combiner #(
|
||||
parameter NUM_MASTERS = 2,
|
||||
parameter PRIORITY = 0
|
||||
) (
|
||||
input wire ctrlport_clk,
|
||||
input wire ctrlport_rst,
|
||||
|
||||
// Requests from multiple masters
|
||||
input wire [ NUM_MASTERS-1:0] s_ctrlport_req_wr,
|
||||
input wire [ NUM_MASTERS-1:0] s_ctrlport_req_rd,
|
||||
input wire [20*NUM_MASTERS-1:0] s_ctrlport_req_addr,
|
||||
input wire [10*NUM_MASTERS-1:0] s_ctrlport_req_portid,
|
||||
input wire [16*NUM_MASTERS-1:0] s_ctrlport_req_rem_epid,
|
||||
input wire [10*NUM_MASTERS-1:0] s_ctrlport_req_rem_portid,
|
||||
input wire [32*NUM_MASTERS-1:0] s_ctrlport_req_data,
|
||||
input wire [ 4*NUM_MASTERS-1:0] s_ctrlport_req_byte_en,
|
||||
input wire [ NUM_MASTERS-1:0] s_ctrlport_req_has_time,
|
||||
input wire [64*NUM_MASTERS-1:0] s_ctrlport_req_time,
|
||||
// Responses to multiple masters
|
||||
output reg [ NUM_MASTERS-1:0] s_ctrlport_resp_ack,
|
||||
output reg [ 2*NUM_MASTERS-1:0] s_ctrlport_resp_status,
|
||||
output reg [32*NUM_MASTERS-1:0] s_ctrlport_resp_data,
|
||||
|
||||
// Request to a single slave
|
||||
output reg m_ctrlport_req_wr,
|
||||
output reg m_ctrlport_req_rd,
|
||||
output reg [19:0] m_ctrlport_req_addr,
|
||||
output reg [ 9:0] m_ctrlport_req_portid,
|
||||
output reg [15:0] m_ctrlport_req_rem_epid,
|
||||
output reg [ 9:0] m_ctrlport_req_rem_portid,
|
||||
output reg [31:0] m_ctrlport_req_data,
|
||||
output reg [ 3:0] m_ctrlport_req_byte_en,
|
||||
output reg m_ctrlport_req_has_time,
|
||||
output reg [63:0] m_ctrlport_req_time,
|
||||
// Response from a single slave
|
||||
input wire m_ctrlport_resp_ack,
|
||||
input wire [ 1:0] m_ctrlport_resp_status,
|
||||
input wire [31:0] m_ctrlport_resp_data
|
||||
);
|
||||
|
||||
reg [$clog2(NUM_MASTERS)-1:0] slave_sel = 0; // Tracks which slave port is
|
||||
// currently being serviced.
|
||||
reg req_load_output = 1'b0;
|
||||
|
||||
// Helper function to convert one hot vector to binary index
|
||||
// (LSB = index 0)
|
||||
function integer one_hot_to_binary(input [NUM_MASTERS-1:0] one_hot_vec);
|
||||
integer i, total;
|
||||
begin
|
||||
total = 0;
|
||||
for (i = 0; i <= NUM_MASTERS-1; i = i + 1) begin
|
||||
if (one_hot_vec[i]) begin
|
||||
total = total + i;
|
||||
end
|
||||
end
|
||||
one_hot_to_binary = total;
|
||||
end
|
||||
endfunction
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Input Registers
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// Latch each request until it can be serviced. Only one request per slave
|
||||
// can be in progress at a time.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
reg [ NUM_MASTERS-1:0] req_valid = 0;
|
||||
reg [ NUM_MASTERS-1:0] req_wr;
|
||||
reg [ NUM_MASTERS-1:0] req_rd;
|
||||
reg [20*NUM_MASTERS-1:0] req_addr;
|
||||
reg [10*NUM_MASTERS-1:0] req_portid;
|
||||
reg [16*NUM_MASTERS-1:0] req_rem_epid;
|
||||
reg [10*NUM_MASTERS-1:0] req_rem_portid;
|
||||
reg [32*NUM_MASTERS-1:0] req_data;
|
||||
reg [ 4*NUM_MASTERS-1:0] req_byte_en;
|
||||
reg [ NUM_MASTERS-1:0] req_has_time;
|
||||
reg [64*NUM_MASTERS-1:0] req_time;
|
||||
|
||||
always @(posedge ctrlport_clk) begin : input_buffer_block
|
||||
integer i;
|
||||
if (ctrlport_rst) begin
|
||||
req_valid <= 0;
|
||||
end else begin : input_reg_gen
|
||||
for (i = 0; i < NUM_MASTERS; i = i + 1) begin
|
||||
if (s_ctrlport_req_wr[i] | s_ctrlport_req_rd[i]) begin
|
||||
// Mark this slave's request valid and save the request information
|
||||
req_valid[i] <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// Clear the active request when it gets output
|
||||
if (req_load_output) begin
|
||||
req_valid[slave_sel] <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Buffer request information without reset
|
||||
for (i = 0; i < NUM_MASTERS; i = i + 1) begin
|
||||
if (s_ctrlport_req_wr[i] | s_ctrlport_req_rd[i]) begin
|
||||
req_wr[i] <= s_ctrlport_req_wr[i];
|
||||
req_rd[i] <= s_ctrlport_req_rd[i];
|
||||
req_addr[20*i+:20] <= s_ctrlport_req_addr[20*i+:20];
|
||||
req_portid[10*i+:10] <= s_ctrlport_req_portid[10*i+:10];
|
||||
req_rem_epid[16*i+:16] <= s_ctrlport_req_rem_epid[16*i+:16];
|
||||
req_rem_portid[10*i+:10] <= s_ctrlport_req_rem_portid[10*i+:10];
|
||||
req_data[32*i+:32] <= s_ctrlport_req_data[32*i+:32];
|
||||
req_byte_en[4*i+:4] <= s_ctrlport_req_byte_en[4*i+:4];
|
||||
req_has_time[i] <= s_ctrlport_req_has_time[i];
|
||||
req_time[64*i+:64] <= s_ctrlport_req_time[64*i+:64];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Arbitration State Machine
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// This state machine tracks which slave port is being serviced and which to
|
||||
// service next. This is done using a counter that simply checks each port in
|
||||
// sequential order and then stops when it finds one that has a valid request.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
reg req_active = 0; // Indicates if there's a request being serviced
|
||||
wire [NUM_MASTERS-1:0] next_slave_one_hot; // one hot for next active request
|
||||
// (used for PRIORITY = 1)
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < NUM_MASTERS; i = i+1) begin : gen_next_slave_one_hot
|
||||
if (i == 0) begin
|
||||
assign next_slave_one_hot[i] = req_valid[i];
|
||||
end else begin
|
||||
assign next_slave_one_hot[i] = req_valid[i] & ~next_slave_one_hot[i-1];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge ctrlport_clk) begin
|
||||
if (ctrlport_rst) begin
|
||||
slave_sel <= 0;
|
||||
req_active <= 1'b0;
|
||||
req_load_output <= 1'b0;
|
||||
end else begin
|
||||
req_load_output <= 1'b0;
|
||||
|
||||
if (req_active) begin
|
||||
// Wait until we get the response before we allow another request
|
||||
if (m_ctrlport_resp_ack) begin
|
||||
req_active <= 1'b0;
|
||||
|
||||
// Go to next slave immediately
|
||||
if(PRIORITY == 1)
|
||||
slave_sel <= one_hot_to_binary(next_slave_one_hot);
|
||||
// Round robin - Go to the next slave so we don't service the same
|
||||
// slave again
|
||||
else if(slave_sel == NUM_MASTERS-1)
|
||||
slave_sel <= 0;
|
||||
else
|
||||
slave_sel <= slave_sel + 1;
|
||||
end
|
||||
end else begin
|
||||
// No active request in progress, so check if there's a new request on
|
||||
// the selected slave.
|
||||
if (req_valid[slave_sel]) begin
|
||||
req_active <= 1'b1;
|
||||
req_load_output <= 1'b1;
|
||||
end else begin
|
||||
// Go to next slave immediately
|
||||
if(PRIORITY == 1)
|
||||
slave_sel <= one_hot_to_binary(next_slave_one_hot);
|
||||
// Round robin - Nothing from this slave, so move to the next slave.
|
||||
else if (slave_sel == NUM_MASTERS-1)
|
||||
slave_sel <= 0;
|
||||
else
|
||||
slave_sel <= slave_sel + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Output Register
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// Here we load the active request for a single clock cycle and demultiplex
|
||||
// the response back to the requesting master.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
always @(posedge ctrlport_clk) begin : output_reg_gen
|
||||
integer i;
|
||||
|
||||
// ---------- Request --------------
|
||||
// Load the active request
|
||||
if (req_load_output) begin
|
||||
m_ctrlport_req_wr <= req_wr [slave_sel];
|
||||
m_ctrlport_req_rd <= req_rd [slave_sel];
|
||||
m_ctrlport_req_addr <= req_addr [20*slave_sel +: 20];
|
||||
m_ctrlport_req_portid <= req_portid [10*slave_sel +: 10];
|
||||
m_ctrlport_req_rem_epid <= req_rem_epid [16*slave_sel +: 16];
|
||||
m_ctrlport_req_rem_portid <= req_rem_portid[10*slave_sel +: 10];
|
||||
m_ctrlport_req_data <= req_data [32*slave_sel +: 32];
|
||||
m_ctrlport_req_byte_en <= req_byte_en [ 4*slave_sel +: 4];
|
||||
m_ctrlport_req_has_time <= req_has_time [slave_sel];
|
||||
m_ctrlport_req_time <= req_time [64*slave_sel +: 64];
|
||||
end else begin
|
||||
m_ctrlport_req_wr <= 1'b0;
|
||||
m_ctrlport_req_rd <= 1'b0;
|
||||
end
|
||||
|
||||
if (ctrlport_rst) begin
|
||||
m_ctrlport_req_wr <= 1'b0;
|
||||
m_ctrlport_req_rd <= 1'b0;
|
||||
end
|
||||
|
||||
// ---------- Response --------------
|
||||
// Output any response to the master that made the request
|
||||
for (i = 0; i < NUM_MASTERS; i = i + 1) begin
|
||||
// Give the response data to all the slaves (no demux, to save logic)
|
||||
s_ctrlport_resp_status[2*i +: 2] <= m_ctrlport_resp_status;
|
||||
s_ctrlport_resp_data[32*i +: 32] <= m_ctrlport_resp_data;
|
||||
|
||||
// Give the ack only to the master that made the request (use a demux)
|
||||
if (ctrlport_rst) begin
|
||||
s_ctrlport_resp_ack[i] <= 1'b0;
|
||||
end else if (i == slave_sel && m_ctrlport_resp_ack) begin
|
||||
s_ctrlport_resp_ack[i] <= 1'b1;
|
||||
end else begin
|
||||
s_ctrlport_resp_ack[i] <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,135 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_decoder
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This block splits a single control port interface into multiple. It is used
|
||||
// when you have a single master that needs to access multiple slaves. For
|
||||
// example, a NoC block where the registers are implemented in multiple
|
||||
// submodules that must be read/written by a single NoC shell.
|
||||
//
|
||||
// This version also implements address decoding. The request is passed to a
|
||||
// slave only if the address falls within that slave's address space. Each
|
||||
// slave is given an address space of 2**ADDR_W and the first slave starts at
|
||||
// address BASE_ADDR. In other words, the request address is partitioned as
|
||||
// shown below.
|
||||
//
|
||||
// |---------------- 32-bit -----------------|
|
||||
// | Base | Port Num | Slave Addr |
|
||||
// |-----------------------------------------|
|
||||
//
|
||||
// When passed to the slave, the base address and port number bits are stripped
|
||||
// from the request address and only the SLAVE_ADDR_W-bit address is passed
|
||||
// through.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// NUM_SLAVES : Number of slave devices that you want to connect to master.
|
||||
// BASE_ADDR : Base address for slave 0. This should be a power-of-2
|
||||
// multiple of the combined slave address spaces.
|
||||
// SLAVE_ADDR_W : Number of address bits to allocate to each slave.
|
||||
//
|
||||
|
||||
module ctrlport_decoder
|
||||
import ctrlport_pkg::*;
|
||||
#(
|
||||
int NUM_SLAVES = 2,
|
||||
int BASE_ADDR = 0,
|
||||
int SLAVE_ADDR_W = 8
|
||||
) (
|
||||
input logic ctrlport_clk,
|
||||
input logic ctrlport_rst,
|
||||
|
||||
// Slave Interface
|
||||
input logic s_ctrlport_req_wr,
|
||||
input logic s_ctrlport_req_rd,
|
||||
input logic [ CTRLPORT_ADDR_W-1:0] s_ctrlport_req_addr,
|
||||
input logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_req_data,
|
||||
input logic [CTRLPORT_BYTE_EN_W-1:0] s_ctrlport_req_byte_en,
|
||||
input logic s_ctrlport_req_has_time,
|
||||
input logic [ CTRLPORT_TIME_W-1:0] s_ctrlport_req_time,
|
||||
output logic s_ctrlport_resp_ack,
|
||||
output logic [ CTRLPORT_STS_W-1:0] s_ctrlport_resp_status,
|
||||
output logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_resp_data,
|
||||
|
||||
// Master Interfaces
|
||||
output logic [ NUM_SLAVES-1:0] m_ctrlport_req_wr,
|
||||
output logic [ NUM_SLAVES-1:0] m_ctrlport_req_rd,
|
||||
output logic [ CTRLPORT_ADDR_W*NUM_SLAVES-1:0] m_ctrlport_req_addr,
|
||||
output logic [ CTRLPORT_DATA_W*NUM_SLAVES-1:0] m_ctrlport_req_data,
|
||||
output logic [CTRLPORT_BYTE_EN_W*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
|
||||
output logic [ NUM_SLAVES-1:0] m_ctrlport_req_has_time,
|
||||
output logic [ CTRLPORT_TIME_W*NUM_SLAVES-1:0] m_ctrlport_req_time,
|
||||
input logic [ NUM_SLAVES-1:0] m_ctrlport_resp_ack,
|
||||
input logic [ CTRLPORT_STS_W*NUM_SLAVES-1:0] m_ctrlport_resp_status,
|
||||
input logic [ CTRLPORT_DATA_W*NUM_SLAVES-1:0] m_ctrlport_resp_data
|
||||
);
|
||||
|
||||
import ctrlport_pkg::*;
|
||||
|
||||
// calculate base addresses
|
||||
typedef int int_array_t[NUM_SLAVES];
|
||||
|
||||
function int_array_t calc_port_base();
|
||||
int_array_t base;
|
||||
for (int i = 0; i < NUM_SLAVES; i++) begin
|
||||
base[i] = BASE_ADDR + i * 2**SLAVE_ADDR_W;
|
||||
end
|
||||
return base;
|
||||
endfunction
|
||||
|
||||
localparam int PORT_BASE [NUM_SLAVES] = calc_port_base();
|
||||
localparam int PORT_SIZE [NUM_SLAVES] = '{default: 2**SLAVE_ADDR_W};
|
||||
|
||||
// Define interfaces
|
||||
ctrlport_if s_ctrlport_if(.clk(ctrlport_clk), .rst(ctrlport_rst));
|
||||
ctrlport_if m_ctrlport_if[NUM_SLAVES](.clk(ctrlport_clk), .rst(ctrlport_rst));
|
||||
|
||||
// Map existing ports to ctrlport_if
|
||||
always_comb begin
|
||||
s_ctrlport_if.req = '0;
|
||||
s_ctrlport_if.req.wr = s_ctrlport_req_wr;
|
||||
s_ctrlport_if.req.rd = s_ctrlport_req_rd;
|
||||
s_ctrlport_if.req.addr = s_ctrlport_req_addr;
|
||||
s_ctrlport_if.req.data = s_ctrlport_req_data;
|
||||
s_ctrlport_if.req.byte_en = s_ctrlport_req_byte_en;
|
||||
s_ctrlport_if.req.has_time = s_ctrlport_req_has_time;
|
||||
s_ctrlport_if.req.timestamp = s_ctrlport_req_time;
|
||||
|
||||
s_ctrlport_resp_ack = s_ctrlport_if.resp.ack;
|
||||
s_ctrlport_resp_status = s_ctrlport_if.resp.status;
|
||||
s_ctrlport_resp_data = s_ctrlport_if.resp.data;
|
||||
end
|
||||
|
||||
// Instantiate ctrlport_if_decoder module
|
||||
ctrlport_if_decoder #(
|
||||
.NUM_SLAVES(NUM_SLAVES),
|
||||
.PORT_BASE(PORT_BASE),
|
||||
.PORT_SIZE(PORT_SIZE)
|
||||
) decoder_inst (
|
||||
.s_ctrlport(s_ctrlport_if),
|
||||
.m_ctrlport(m_ctrlport_if)
|
||||
);
|
||||
|
||||
// Unpack ctrlport_if to output port
|
||||
for (genvar i = 0; i < NUM_SLAVES; i++) begin : output_gen
|
||||
always_comb begin
|
||||
m_ctrlport_req_wr[i] = m_ctrlport_if[i].req.wr;
|
||||
m_ctrlport_req_rd[i] = m_ctrlport_if[i].req.rd;
|
||||
m_ctrlport_req_addr[i*CTRLPORT_ADDR_W +: CTRLPORT_ADDR_W] = m_ctrlport_if[i].req.addr;
|
||||
m_ctrlport_req_data[i*CTRLPORT_DATA_W +: CTRLPORT_DATA_W] = m_ctrlport_if[i].req.data;
|
||||
m_ctrlport_req_byte_en[i*CTRLPORT_BYTE_EN_W +: CTRLPORT_BYTE_EN_W] = m_ctrlport_if[i].req.byte_en;
|
||||
m_ctrlport_req_has_time[i] = m_ctrlport_if[i].req.has_time;
|
||||
m_ctrlport_req_time[i*CTRLPORT_TIME_W +: CTRLPORT_TIME_W] = m_ctrlport_if[i].req.timestamp;
|
||||
|
||||
m_ctrlport_if[i].resp.ack = m_ctrlport_resp_ack[i];
|
||||
m_ctrlport_if[i].resp.status = ctrlport_status_t'(m_ctrlport_resp_status[i*CTRLPORT_STS_W +: CTRLPORT_STS_W]);
|
||||
m_ctrlport_if[i].resp.data = m_ctrlport_resp_data[i*CTRLPORT_DATA_W +: CTRLPORT_DATA_W];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,154 +0,0 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_decoder
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This block splits a single control port interface into multiple. It is used
|
||||
// when you have a single master that needs to access multiple slaves. For
|
||||
// example, a NoC block where the registers are implemented in multiple
|
||||
// submodules that must be read/written by a single NoC shell.
|
||||
//
|
||||
// This version also implements address decoding. The request is passed to a
|
||||
// slave only if the address falls within that slave's address space. Each
|
||||
// slave is given an address space of 2**ADDR_W and the first slave starts at
|
||||
// address BASE_ADDR. In other words, the request address is partitioned as
|
||||
// shown below.
|
||||
//
|
||||
// |---------------- 32-bit -----------------|
|
||||
// | Base | Port Num | Slave Addr |
|
||||
// |-----------------------------------------|
|
||||
//
|
||||
// When passed to the slave, the base address and port number bits are stripped
|
||||
// from the request address and only the SLAVE_ADDR_W-bit address is passed
|
||||
// through.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// NUM_SLAVES : Number of slave devices that you want to connect to master.
|
||||
// BASE_ADDR : Base address for slave 0. This should be a power-of-2
|
||||
// multiple of the combined slave address spaces.
|
||||
// SLAVE_ADDR_W : Number of address bits to allocate to each slave.
|
||||
//
|
||||
|
||||
module ctrlport_decoder #(
|
||||
parameter NUM_SLAVES = 2,
|
||||
parameter BASE_ADDR = 0,
|
||||
parameter SLAVE_ADDR_W = 8
|
||||
) (
|
||||
input wire ctrlport_clk,
|
||||
input wire ctrlport_rst,
|
||||
|
||||
// Slave Interface
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
input wire [ 3:0] s_ctrlport_req_byte_en,
|
||||
input wire s_ctrlport_req_has_time,
|
||||
input wire [63:0] s_ctrlport_req_time,
|
||||
output reg s_ctrlport_resp_ack = 1'b0,
|
||||
output reg [ 1:0] s_ctrlport_resp_status,
|
||||
output reg [31:0] s_ctrlport_resp_data,
|
||||
|
||||
// Master Interfaces
|
||||
output reg [ NUM_SLAVES-1:0] m_ctrlport_req_wr = 0,
|
||||
output reg [ NUM_SLAVES-1:0] m_ctrlport_req_rd = 0,
|
||||
output reg [20*NUM_SLAVES-1:0] m_ctrlport_req_addr = 0,
|
||||
output reg [32*NUM_SLAVES-1:0] m_ctrlport_req_data,
|
||||
output reg [ 4*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
|
||||
output reg [ NUM_SLAVES-1:0] m_ctrlport_req_has_time,
|
||||
output reg [64*NUM_SLAVES-1:0] m_ctrlport_req_time,
|
||||
input wire [ NUM_SLAVES-1:0] m_ctrlport_resp_ack,
|
||||
input wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
|
||||
input wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
|
||||
);
|
||||
|
||||
localparam PORT_NUM_W = $clog2(NUM_SLAVES);
|
||||
localparam PORT_NUM_POS = SLAVE_ADDR_W;
|
||||
localparam BASE_ADDR_W = 20 - (SLAVE_ADDR_W + PORT_NUM_W);
|
||||
localparam BASE_ADDR_POS = SLAVE_ADDR_W + PORT_NUM_W;
|
||||
localparam [19:0] BASE_ADDR_MASK = { BASE_ADDR_W {1'b1}} << BASE_ADDR_POS;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Split the requests among the slaves
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire [NUM_SLAVES-1:0] decoder;
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
|
||||
// Check if the upper bits of the request address match each slave. If the
|
||||
// address matches, set the corresponding decoder[] bit.
|
||||
if (PORT_NUM_W == 0) begin
|
||||
// Only one port in this case, so there are no port number bits to check
|
||||
assign decoder[i] = ((s_ctrlport_req_addr & BASE_ADDR_MASK) == BASE_ADDR);
|
||||
end else begin
|
||||
assign decoder[i] = ((s_ctrlport_req_addr & BASE_ADDR_MASK) == BASE_ADDR) &&
|
||||
(s_ctrlport_req_addr[PORT_NUM_POS +: PORT_NUM_W] == i);
|
||||
end
|
||||
|
||||
always @(posedge ctrlport_clk) begin
|
||||
if (ctrlport_rst) begin
|
||||
m_ctrlport_req_wr[i] <= 1'b0;
|
||||
m_ctrlport_req_rd[i] <= 1'b0;
|
||||
end else begin
|
||||
// Mask WR and RD based on address decoding
|
||||
m_ctrlport_req_wr[i] <= s_ctrlport_req_wr & decoder[i];
|
||||
m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & decoder[i];
|
||||
end
|
||||
|
||||
// Other values pass through to all slaves, but should be ignored
|
||||
// unless the corresponding WR or RD is not asserted.
|
||||
m_ctrlport_req_data [32*i +: 32] <= s_ctrlport_req_data;
|
||||
m_ctrlport_req_byte_en [4*i +: 4] <= s_ctrlport_req_byte_en;
|
||||
m_ctrlport_req_has_time[i] <= s_ctrlport_req_has_time;
|
||||
m_ctrlport_req_time [64*i +: 64] <= s_ctrlport_req_time;
|
||||
|
||||
// Pass through only the relevant slave bits
|
||||
m_ctrlport_req_addr[20*i+:20] <= 20'b0;
|
||||
m_ctrlport_req_addr[20*i+:SLAVE_ADDR_W] <= s_ctrlport_req_addr[SLAVE_ADDR_W-1:0];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Decode the responses
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
reg [31:0] data;
|
||||
reg [ 1:0] status;
|
||||
reg ack = 0;
|
||||
|
||||
// Take the responses and mask them with ack, then OR them together
|
||||
always @(*) begin : comb_decode
|
||||
integer s;
|
||||
data = 0;
|
||||
status = 0;
|
||||
ack = 0;
|
||||
for (s = 0; s < NUM_SLAVES; s = s+1) begin
|
||||
data = data | (m_ctrlport_resp_data [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
|
||||
status = status | (m_ctrlport_resp_status[s* 2 +: 2] & { 2{m_ctrlport_resp_ack[s]}});
|
||||
ack = ack | m_ctrlport_resp_ack[s];
|
||||
end
|
||||
end
|
||||
|
||||
// Register the output to break combinatorial path
|
||||
always @(posedge ctrlport_clk) begin
|
||||
if (ctrlport_rst) begin
|
||||
s_ctrlport_resp_ack <= 0;
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= ack;
|
||||
end
|
||||
|
||||
s_ctrlport_resp_data <= data;
|
||||
s_ctrlport_resp_status <= status;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,157 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_decoder_param
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This block splits a single control port interface into multiple. It is
|
||||
// used when you have a single master that needs to access multiple slaves.
|
||||
// For example, a NoC block where the registers are implemented in multiple
|
||||
// submodules that must be read/written by a single NoC shell.
|
||||
//
|
||||
// This version also implements address decoding. The request is passed to a
|
||||
// slave only if the address falls within that slave's address space. Each
|
||||
// slave can have a unique base address and address space size. The address
|
||||
// space is broken up as follows.
|
||||
//
|
||||
// PORT_BASE[0*20 +: 20] = Port 0 base address
|
||||
// │ ┐
|
||||
// │ ├── 2**PORT_ADDR_W[0*32 +: 32] bytes for slave 0
|
||||
// │ ┘
|
||||
// .
|
||||
// .
|
||||
// PORT_BASE[1*20 +: 20] = Port 1 base address
|
||||
// │ ┐
|
||||
// │ ├── 2**PORT_ADDR_W[1*32 +: 32] bytes for slave 1
|
||||
// │ ┘
|
||||
// .
|
||||
// .
|
||||
//
|
||||
// When passed to the slave, the base address is stripped from the request
|
||||
// address so that only the PORT_ADDR_W-bit address is passed through.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// NUM_SLAVES : The number of slaves to connect to a master.
|
||||
// PORT_BASE : Base addresses to use fore each slave. This is a
|
||||
// concatenation of 20-bit addresses, where the right-most
|
||||
// (least-significant) 20 bits corresponds to slave 0. Each
|
||||
// address must be a multiple of 2**PORT_ADDR_W, where
|
||||
// PORT_ADDR_W is the number of address bits allocated to that
|
||||
// slave.
|
||||
// PORT_ADDR_W : Number of address bits to allocate to each slave. This is a
|
||||
// concatenation of 32-bit integers, where the right-most
|
||||
// (least-significant) 32 bits corresponds to the address space
|
||||
// for slave 0.
|
||||
//
|
||||
|
||||
module ctrlport_decoder_param
|
||||
import ctrlport_pkg::*;
|
||||
#(
|
||||
int NUM_SLAVES = 4,
|
||||
bit [CTRLPORT_ADDR_W*NUM_SLAVES-1:0] PORT_BASE = { 20'h300, 20'h200, 20'h100, 20'h000 },
|
||||
bit [ 32*NUM_SLAVES-1:0] PORT_ADDR_W = { 32'd8, 32'd8, 32'd8, 32'd8 }
|
||||
) (
|
||||
input logic ctrlport_clk,
|
||||
input logic ctrlport_rst,
|
||||
|
||||
// Slave Interface
|
||||
input logic s_ctrlport_req_wr,
|
||||
input logic s_ctrlport_req_rd,
|
||||
input logic [ CTRLPORT_ADDR_W-1:0] s_ctrlport_req_addr,
|
||||
input logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_req_data,
|
||||
input logic [CTRLPORT_BYTE_EN_W-1:0] s_ctrlport_req_byte_en,
|
||||
input logic s_ctrlport_req_has_time,
|
||||
input logic [ CTRLPORT_TIME_W-1:0] s_ctrlport_req_time,
|
||||
output logic s_ctrlport_resp_ack,
|
||||
output logic [ CTRLPORT_STS_W-1:0] s_ctrlport_resp_status,
|
||||
output logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_resp_data,
|
||||
|
||||
// Master Interfaces
|
||||
output logic [ NUM_SLAVES-1:0] m_ctrlport_req_wr,
|
||||
output logic [ NUM_SLAVES-1:0] m_ctrlport_req_rd,
|
||||
output logic [ CTRLPORT_ADDR_W*NUM_SLAVES-1:0] m_ctrlport_req_addr,
|
||||
output logic [ CTRLPORT_DATA_W*NUM_SLAVES-1:0] m_ctrlport_req_data,
|
||||
output logic [CTRLPORT_BYTE_EN_W*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
|
||||
output logic [ NUM_SLAVES-1:0] m_ctrlport_req_has_time,
|
||||
output logic [ CTRLPORT_TIME_W*NUM_SLAVES-1:0] m_ctrlport_req_time,
|
||||
input logic [ NUM_SLAVES-1:0] m_ctrlport_resp_ack,
|
||||
input logic [ CTRLPORT_STS_W*NUM_SLAVES-1:0] m_ctrlport_resp_status,
|
||||
input logic [ CTRLPORT_DATA_W*NUM_SLAVES-1:0] m_ctrlport_resp_data
|
||||
);
|
||||
|
||||
import ctrlport_pkg::*;
|
||||
|
||||
// calculate port base address and size
|
||||
typedef int int_array_t[NUM_SLAVES];
|
||||
|
||||
function int_array_t calc_port_base();
|
||||
int_array_t base;
|
||||
for (int i = 0; i < NUM_SLAVES; i++) begin
|
||||
base[i] = PORT_BASE[i*20 +: 20];
|
||||
end
|
||||
return base;
|
||||
endfunction
|
||||
|
||||
function int_array_t calc_port_size();
|
||||
int_array_t size;
|
||||
for (int i = 0; i < NUM_SLAVES; i++) begin
|
||||
size[i] = 2**PORT_ADDR_W[i*32 +: 32];
|
||||
end
|
||||
return size;
|
||||
endfunction
|
||||
|
||||
localparam int PORT_BASE_INT [NUM_SLAVES] = calc_port_base();
|
||||
localparam int PORT_SIZE_INT [NUM_SLAVES] = calc_port_size();
|
||||
|
||||
// Define interfaces
|
||||
ctrlport_if s_ctrlport_if(.clk(ctrlport_clk), .rst(ctrlport_rst));
|
||||
ctrlport_if m_ctrlport_if[NUM_SLAVES](.clk(ctrlport_clk), .rst(ctrlport_rst));
|
||||
|
||||
// Map existing ports to ctrlport_if
|
||||
always_comb begin
|
||||
s_ctrlport_if.req = '0;
|
||||
s_ctrlport_if.req.wr = s_ctrlport_req_wr;
|
||||
s_ctrlport_if.req.rd = s_ctrlport_req_rd;
|
||||
s_ctrlport_if.req.addr = s_ctrlport_req_addr;
|
||||
s_ctrlport_if.req.data = s_ctrlport_req_data;
|
||||
s_ctrlport_if.req.byte_en = s_ctrlport_req_byte_en;
|
||||
s_ctrlport_if.req.has_time = s_ctrlport_req_has_time;
|
||||
s_ctrlport_if.req.timestamp = s_ctrlport_req_time;
|
||||
|
||||
s_ctrlport_resp_ack = s_ctrlport_if.resp.ack;
|
||||
s_ctrlport_resp_status = s_ctrlport_if.resp.status;
|
||||
s_ctrlport_resp_data = s_ctrlport_if.resp.data;
|
||||
end
|
||||
|
||||
// Instantiate ctrlport_if_decoder module
|
||||
ctrlport_if_decoder #(
|
||||
.NUM_SLAVES(NUM_SLAVES),
|
||||
.PORT_BASE(PORT_BASE_INT),
|
||||
.PORT_SIZE(PORT_SIZE_INT)
|
||||
) decoder_inst (
|
||||
.s_ctrlport(s_ctrlport_if),
|
||||
.m_ctrlport(m_ctrlport_if)
|
||||
);
|
||||
|
||||
// Unpack ctrlport_if to output port
|
||||
for (genvar i = 0; i < NUM_SLAVES; i++) begin : output_gen
|
||||
always_comb begin
|
||||
m_ctrlport_req_wr[i] = m_ctrlport_if[i].req.wr;
|
||||
m_ctrlport_req_rd[i] = m_ctrlport_if[i].req.rd;
|
||||
m_ctrlport_req_addr[i*CTRLPORT_ADDR_W +: CTRLPORT_ADDR_W] = m_ctrlport_if[i].req.addr;
|
||||
m_ctrlport_req_data[i*CTRLPORT_DATA_W +: CTRLPORT_DATA_W] = m_ctrlport_if[i].req.data;
|
||||
m_ctrlport_req_byte_en[i*CTRLPORT_BYTE_EN_W +: CTRLPORT_BYTE_EN_W] = m_ctrlport_if[i].req.byte_en;
|
||||
m_ctrlport_req_has_time[i] = m_ctrlport_if[i].req.has_time;
|
||||
m_ctrlport_req_time[i*CTRLPORT_TIME_W +: CTRLPORT_TIME_W] = m_ctrlport_if[i].req.timestamp;
|
||||
|
||||
m_ctrlport_if[i].resp.ack = m_ctrlport_resp_ack[i];
|
||||
m_ctrlport_if[i].resp.status = ctrlport_status_t'(m_ctrlport_resp_status[i*CTRLPORT_STS_W +: CTRLPORT_STS_W]);
|
||||
m_ctrlport_if[i].resp.data = m_ctrlport_resp_data[i*CTRLPORT_DATA_W +: CTRLPORT_DATA_W];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,171 +0,0 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_decoder_param
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This block splits a single control port interface into multiple. It is
|
||||
// used when you have a single master that needs to access multiple slaves.
|
||||
// For example, a NoC block where the registers are implemented in multiple
|
||||
// submodules that must be read/written by a single NoC shell.
|
||||
//
|
||||
// This version also implements address decoding. The request is passed to a
|
||||
// slave only if the address falls within that slave's address space. Each
|
||||
// slave can have a unique base address and address space size. The address
|
||||
// space is broken up as follows.
|
||||
//
|
||||
// PORT_BASE[0*20 +: 20] = Port 0 base address
|
||||
// │ ┐
|
||||
// │ ├── 2**PORT_ADDR_W[0*32 +: 32] bytes for slave 0
|
||||
// │ ┘
|
||||
// .
|
||||
// .
|
||||
// PORT_BASE[1*20 +: 20] = Port 1 base address
|
||||
// │ ┐
|
||||
// │ ├── 2**PORT_ADDR_W[1*32 +: 32] bytes for slave 1
|
||||
// │ ┘
|
||||
// .
|
||||
// .
|
||||
//
|
||||
// When passed to the slave, the base address is stripped from the request
|
||||
// address so that only the PORT_ADDR_W-bit address is passed through.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// NUM_SLAVES : The number of slaves to connect to a master.
|
||||
//
|
||||
// PORT_BASE : Base addresses to use fore each slave. This is a
|
||||
// concatenation of 20-bit addresses, where the right-most
|
||||
// (least-significant) 20 bits corresponds to slave 0. Each
|
||||
// address must be a multiple of 2**PORT_ADDR_W, where
|
||||
// PORT_ADDR_W is the number of address bits allocated to that
|
||||
// slave.
|
||||
//
|
||||
// PORT_ADDR_W : Number of address bits to allocate to each slave. This is a
|
||||
// concatenation of 32-bit integers, where the right-most
|
||||
// (least-significant) 32 bits corresponds to the address space
|
||||
// for slave 0.
|
||||
//
|
||||
|
||||
module ctrlport_decoder_param #(
|
||||
parameter NUM_SLAVES = 4,
|
||||
parameter PORT_BASE = { 20'h300, 20'h200, 20'h100, 20'h000 },
|
||||
parameter PORT_ADDR_W = { 32'd8, 32'd8, 32'd8, 32'd8 }
|
||||
) (
|
||||
input wire ctrlport_clk,
|
||||
input wire ctrlport_rst,
|
||||
|
||||
// Slave Interface
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
input wire [ 3:0] s_ctrlport_req_byte_en,
|
||||
input wire s_ctrlport_req_has_time,
|
||||
input wire [63:0] s_ctrlport_req_time,
|
||||
output reg s_ctrlport_resp_ack = 1'b0,
|
||||
output reg [ 1:0] s_ctrlport_resp_status,
|
||||
output reg [31:0] s_ctrlport_resp_data,
|
||||
|
||||
// Master Interfaces
|
||||
output reg [ NUM_SLAVES-1:0] m_ctrlport_req_wr = 0,
|
||||
output reg [ NUM_SLAVES-1:0] m_ctrlport_req_rd = 0,
|
||||
output reg [20*NUM_SLAVES-1:0] m_ctrlport_req_addr = 0,
|
||||
output reg [32*NUM_SLAVES-1:0] m_ctrlport_req_data,
|
||||
output reg [ 4*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
|
||||
output reg [ NUM_SLAVES-1:0] m_ctrlport_req_has_time,
|
||||
output reg [64*NUM_SLAVES-1:0] m_ctrlport_req_time,
|
||||
input wire [ NUM_SLAVES-1:0] m_ctrlport_resp_ack,
|
||||
input wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
|
||||
input wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
|
||||
);
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Address Decode Logic
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// Check if the upper bits of the request address match each slave. If the
|
||||
// address matches, set the corresponding dec_mask[] bit.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire [NUM_SLAVES-1:0] dec_mask; // Address decoder mask
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
|
||||
for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_dec_mask
|
||||
localparam [19:0] BASE_ADDR = PORT_BASE [i*20 +: 20];
|
||||
localparam [31:0] ADDR_W = PORT_ADDR_W[i*32 +: 32];
|
||||
assign dec_mask[i] = ~|((s_ctrlport_req_addr ^ BASE_ADDR) & ((~0) << ADDR_W));
|
||||
end
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Split the requests among the slaves
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
|
||||
localparam [31:0] ADDR_W = PORT_ADDR_W[i*32 +: 32];
|
||||
|
||||
always @(posedge ctrlport_clk) begin
|
||||
if (ctrlport_rst) begin
|
||||
m_ctrlport_req_wr[i] <= 1'b0;
|
||||
m_ctrlport_req_rd[i] <= 1'b0;
|
||||
end else begin
|
||||
// Mask WR and RD based on address decoding
|
||||
m_ctrlport_req_wr[i] <= s_ctrlport_req_wr & dec_mask[i];
|
||||
m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & dec_mask[i];
|
||||
end
|
||||
|
||||
// Other values pass through to all slaves, but should be ignored
|
||||
// unless WR or RD is asserted.
|
||||
m_ctrlport_req_data [32*i +: 32] <= s_ctrlport_req_data;
|
||||
m_ctrlport_req_byte_en [4*i +: 4] <= s_ctrlport_req_byte_en;
|
||||
m_ctrlport_req_has_time[i] <= s_ctrlport_req_has_time;
|
||||
m_ctrlport_req_time [64*i +: 64] <= s_ctrlport_req_time;
|
||||
|
||||
// Mask the address bits to that of the slaves address space.
|
||||
m_ctrlport_req_addr[20*i +: 20] <= 20'b0;
|
||||
m_ctrlport_req_addr[20*i +: ADDR_W] <= s_ctrlport_req_addr[ADDR_W-1 : 0];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Decode the responses
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
reg [31:0] data;
|
||||
reg [ 1:0] status;
|
||||
reg ack = 0;
|
||||
|
||||
// Take the responses and mask them with ack, then OR them together
|
||||
always @(*) begin : comb_decode
|
||||
integer s;
|
||||
data = 0;
|
||||
status = 0;
|
||||
ack = 0;
|
||||
for (s = 0; s < NUM_SLAVES; s = s+1) begin
|
||||
data = data | (m_ctrlport_resp_data [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
|
||||
status = status | (m_ctrlport_resp_status[s* 2 +: 2] & { 2{m_ctrlport_resp_ack[s]}});
|
||||
ack = ack | m_ctrlport_resp_ack[s];
|
||||
end
|
||||
end
|
||||
|
||||
// Register the output to break combinatorial path
|
||||
always @(posedge ctrlport_clk) begin
|
||||
if (ctrlport_rst) begin
|
||||
s_ctrlport_resp_ack <= 0;
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= ack;
|
||||
end
|
||||
|
||||
s_ctrlport_resp_data <= data;
|
||||
s_ctrlport_resp_status <= status;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,110 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_splitter
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This block splits a single control port interface into multiple. It is used
|
||||
// when you have a single master that needs to access multiple slaves. For
|
||||
// example, a NoC block where the registers are implemented in multiple
|
||||
// submodules that must be read/written by a single NoC shell.
|
||||
//
|
||||
// Note that this block does not do any address decoding, so the connected
|
||||
// slaves must use non-overlapping address spaces.
|
||||
//
|
||||
// This module takes the request received by its single slave interface and
|
||||
// outputs it on all its master interfaces. In the opposite direction, it takes
|
||||
// the responses received by its multiple master interfaces and combines them
|
||||
// into a single response on its slave interface. This is done by using the ack
|
||||
// bit of each response to mask the other bits of the response, then OR'ing all
|
||||
// of the masked responses together onto a single response bus. This is valid
|
||||
// because only one block is allowed to respond to a single request.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// NUM_SLAVES : The number of slaves you want to connect to a master.
|
||||
//
|
||||
|
||||
|
||||
module ctrlport_splitter
|
||||
import ctrlport_pkg::*;
|
||||
#(
|
||||
int NUM_SLAVES = 2
|
||||
) (
|
||||
input logic ctrlport_clk,
|
||||
input logic ctrlport_rst,
|
||||
|
||||
// Slave Interface
|
||||
input logic s_ctrlport_req_wr,
|
||||
input logic s_ctrlport_req_rd,
|
||||
input logic [ CTRLPORT_ADDR_W-1:0] s_ctrlport_req_addr,
|
||||
input logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_req_data,
|
||||
input logic [CTRLPORT_BYTE_EN_W-1:0] s_ctrlport_req_byte_en,
|
||||
input logic s_ctrlport_req_has_time,
|
||||
input logic [ CTRLPORT_TIME_W-1:0] s_ctrlport_req_time,
|
||||
output logic s_ctrlport_resp_ack,
|
||||
output logic [ CTRLPORT_STS_W-1:0] s_ctrlport_resp_status,
|
||||
output logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_resp_data,
|
||||
|
||||
// Master Interfaces
|
||||
output logic [ NUM_SLAVES-1:0] m_ctrlport_req_wr,
|
||||
output logic [ NUM_SLAVES-1:0] m_ctrlport_req_rd,
|
||||
output logic [ CTRLPORT_ADDR_W*NUM_SLAVES-1:0] m_ctrlport_req_addr,
|
||||
output logic [ CTRLPORT_DATA_W*NUM_SLAVES-1:0] m_ctrlport_req_data,
|
||||
output logic [CTRLPORT_BYTE_EN_W*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
|
||||
output logic [ NUM_SLAVES-1:0] m_ctrlport_req_has_time,
|
||||
output logic [ CTRLPORT_TIME_W*NUM_SLAVES-1:0] m_ctrlport_req_time,
|
||||
input logic [ NUM_SLAVES-1:0] m_ctrlport_resp_ack,
|
||||
input logic [ CTRLPORT_STS_W*NUM_SLAVES-1:0] m_ctrlport_resp_status,
|
||||
input logic [ CTRLPORT_DATA_W*NUM_SLAVES-1:0] m_ctrlport_resp_data
|
||||
);
|
||||
|
||||
// Define interfaces
|
||||
ctrlport_if s_ctrlport_if(.clk(ctrlport_clk), .rst(ctrlport_rst));
|
||||
ctrlport_if m_ctrlport_if[NUM_SLAVES](.clk(ctrlport_clk), .rst(ctrlport_rst));
|
||||
|
||||
// Map existing ports to ctrlport_if
|
||||
always_comb begin
|
||||
s_ctrlport_if.req = '0;
|
||||
s_ctrlport_if.req.wr = s_ctrlport_req_wr;
|
||||
s_ctrlport_if.req.rd = s_ctrlport_req_rd;
|
||||
s_ctrlport_if.req.addr = s_ctrlport_req_addr;
|
||||
s_ctrlport_if.req.data = s_ctrlport_req_data;
|
||||
s_ctrlport_if.req.byte_en = s_ctrlport_req_byte_en;
|
||||
s_ctrlport_if.req.has_time = s_ctrlport_req_has_time;
|
||||
s_ctrlport_if.req.timestamp = s_ctrlport_req_time;
|
||||
|
||||
s_ctrlport_resp_ack = s_ctrlport_if.resp.ack;
|
||||
s_ctrlport_resp_status = s_ctrlport_if.resp.status;
|
||||
s_ctrlport_resp_data = s_ctrlport_if.resp.data;
|
||||
end
|
||||
|
||||
// Instantiate ctrlport_if_splitter module
|
||||
ctrlport_if_splitter #(
|
||||
.NUM_SLAVES(NUM_SLAVES)
|
||||
) splitter_inst (
|
||||
.s_ctrlport(s_ctrlport_if),
|
||||
.m_ctrlport(m_ctrlport_if)
|
||||
);
|
||||
|
||||
// Unpack ctrlport_if to output port
|
||||
for (genvar i = 0; i < NUM_SLAVES; i++) begin : output_gen
|
||||
always_comb begin
|
||||
m_ctrlport_req_wr[i] = m_ctrlport_if[i].req.wr;
|
||||
m_ctrlport_req_rd[i] = m_ctrlport_if[i].req.rd;
|
||||
m_ctrlport_req_addr[i*CTRLPORT_ADDR_W +: CTRLPORT_ADDR_W] = m_ctrlport_if[i].req.addr;
|
||||
m_ctrlport_req_data[i*CTRLPORT_DATA_W +: CTRLPORT_DATA_W] = m_ctrlport_if[i].req.data;
|
||||
m_ctrlport_req_byte_en[i*CTRLPORT_BYTE_EN_W +: CTRLPORT_BYTE_EN_W] = m_ctrlport_if[i].req.byte_en;
|
||||
m_ctrlport_req_has_time[i] = m_ctrlport_if[i].req.has_time;
|
||||
m_ctrlport_req_time[i*CTRLPORT_TIME_W +: CTRLPORT_TIME_W] = m_ctrlport_if[i].req.timestamp;
|
||||
|
||||
m_ctrlport_if[i].resp.ack = m_ctrlport_resp_ack[i];
|
||||
m_ctrlport_if[i].resp.status = ctrlport_status_t'(m_ctrlport_resp_status[i*CTRLPORT_STS_W +: CTRLPORT_STS_W]);
|
||||
m_ctrlport_if[i].resp.data = m_ctrlport_resp_data[i*CTRLPORT_DATA_W +: CTRLPORT_DATA_W];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,130 +0,0 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_splitter
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This block splits a single control port interface into multiple. It is used
|
||||
// when you have a single master that needs to access multiple slaves. For
|
||||
// example, a NoC block where the registers are implemented in multiple
|
||||
// submodules that must be read/written by a single NoC shell.
|
||||
//
|
||||
// Note that this block does not do any address decoding, so the connected
|
||||
// slaves must use non-overlapping address spaces.
|
||||
//
|
||||
// This module takes the request received by its single slave interface and
|
||||
// outputs it on all its master interfaces. In the opposite direction, it takes
|
||||
// the responses received by its multiple master interfaces and combines them
|
||||
// into a single response on its slave interface. This is done by using the ack
|
||||
// bit of each response to mask the other bits of the response, then OR'ing all
|
||||
// of the masked responses together onto a single response bus. This is valid
|
||||
// because only one block is allowed to respond to a single request.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// NUM_SLAVES : The number of slaves you want to connect to a master.
|
||||
//
|
||||
|
||||
|
||||
module ctrlport_splitter #(
|
||||
parameter NUM_SLAVES = 2
|
||||
) (
|
||||
input wire ctrlport_clk,
|
||||
input wire ctrlport_rst,
|
||||
|
||||
// Slave Interface
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
input wire [ 3:0] s_ctrlport_req_byte_en,
|
||||
input wire s_ctrlport_req_has_time,
|
||||
input wire [63:0] s_ctrlport_req_time,
|
||||
output reg s_ctrlport_resp_ack = 1'b0,
|
||||
output reg [ 1:0] s_ctrlport_resp_status,
|
||||
output reg [31:0] s_ctrlport_resp_data,
|
||||
|
||||
// Master Interfaces
|
||||
output wire [ NUM_SLAVES-1:0] m_ctrlport_req_wr,
|
||||
output wire [ NUM_SLAVES-1:0] m_ctrlport_req_rd,
|
||||
output wire [20*NUM_SLAVES-1:0] m_ctrlport_req_addr,
|
||||
output wire [32*NUM_SLAVES-1:0] m_ctrlport_req_data,
|
||||
output wire [ 4*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
|
||||
output wire [ NUM_SLAVES-1:0] m_ctrlport_req_has_time,
|
||||
output wire [64*NUM_SLAVES-1:0] m_ctrlport_req_time,
|
||||
input wire [ NUM_SLAVES-1:0] m_ctrlport_resp_ack,
|
||||
input wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
|
||||
input wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
|
||||
);
|
||||
|
||||
generate
|
||||
if (NUM_SLAVES == 1) begin : gen_no_split
|
||||
// No logic is needed if only one slave is going to be connected
|
||||
assign m_ctrlport_req_wr = s_ctrlport_req_wr;
|
||||
assign m_ctrlport_req_rd = s_ctrlport_req_rd;
|
||||
assign m_ctrlport_req_addr = s_ctrlport_req_addr;
|
||||
assign m_ctrlport_req_data = s_ctrlport_req_data;
|
||||
assign m_ctrlport_req_byte_en = s_ctrlport_req_byte_en;
|
||||
assign m_ctrlport_req_has_time = s_ctrlport_req_has_time;
|
||||
assign m_ctrlport_req_time = s_ctrlport_req_time;
|
||||
always @(*) begin
|
||||
s_ctrlport_resp_ack = m_ctrlport_resp_ack;
|
||||
s_ctrlport_resp_status = m_ctrlport_resp_status;
|
||||
s_ctrlport_resp_data = m_ctrlport_resp_data;
|
||||
end
|
||||
|
||||
end else begin : gen_splitter
|
||||
//---------------------------------------------------------------------------
|
||||
// Split the requests among the slaves
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
genvar i;
|
||||
for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
|
||||
// No special logic is required to split the requests from the master among
|
||||
// multiple slaves.
|
||||
assign m_ctrlport_req_wr[i] = s_ctrlport_req_wr;
|
||||
assign m_ctrlport_req_rd[i] = s_ctrlport_req_rd;
|
||||
assign m_ctrlport_req_addr[20*i+:20] = s_ctrlport_req_addr;
|
||||
assign m_ctrlport_req_data[32*i+:32] = s_ctrlport_req_data;
|
||||
assign m_ctrlport_req_byte_en[4*i+:4] = s_ctrlport_req_byte_en;
|
||||
assign m_ctrlport_req_has_time[i] = s_ctrlport_req_has_time;
|
||||
assign m_ctrlport_req_time[64*i+:64] = s_ctrlport_req_time;
|
||||
end
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Decode the responses
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
reg [31:0] data;
|
||||
reg [ 1:0] status;
|
||||
reg ack = 0;
|
||||
|
||||
// Take the responses and mask them with ack, then OR them together
|
||||
always @(*) begin : comb_decode
|
||||
integer s;
|
||||
data = 0;
|
||||
status = 0;
|
||||
ack = 0;
|
||||
for (s = 0; s < NUM_SLAVES; s = s+1) begin
|
||||
data = data | (m_ctrlport_resp_data [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
|
||||
status = status | (m_ctrlport_resp_status[s* 2 +: 2] & { 2{m_ctrlport_resp_ack[s]}});
|
||||
ack = ack | m_ctrlport_resp_ack[s];
|
||||
end
|
||||
end
|
||||
|
||||
// Register the output to break combinatorial path
|
||||
always @(posedge ctrlport_clk) begin : response_reg
|
||||
s_ctrlport_resp_data <= data;
|
||||
s_ctrlport_resp_status <= status;
|
||||
s_ctrlport_resp_ack <= ack;
|
||||
|
||||
if (ctrlport_rst) begin
|
||||
s_ctrlport_resp_ack <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
@@ -0,0 +1,62 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_terminator.v
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// Returns an error for all ctrlport requests in given address range.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// START_ADDRESS: First address to generate response for
|
||||
// LAST_ADDRESS: Last address (including) to generate response for
|
||||
//
|
||||
|
||||
module ctrlport_terminator
|
||||
import ctrlport_pkg::*;
|
||||
#(
|
||||
int START_ADDRESS = 0,
|
||||
int LAST_ADDRESS = 32
|
||||
)(
|
||||
//---------------------------------------------------------------
|
||||
// ControlPort slave
|
||||
//---------------------------------------------------------------
|
||||
input logic ctrlport_clk,
|
||||
input logic ctrlport_rst,
|
||||
|
||||
input logic s_ctrlport_req_wr,
|
||||
input logic s_ctrlport_req_rd,
|
||||
input logic [CTRLPORT_ADDR_W-1:0] s_ctrlport_req_addr,
|
||||
input logic [CTRLPORT_DATA_W-1:0] s_ctrlport_req_data,
|
||||
output logic s_ctrlport_resp_ack,
|
||||
output logic [ CTRLPORT_STS_W-1:0] s_ctrlport_resp_status,
|
||||
output logic [CTRLPORT_DATA_W-1:0] s_ctrlport_resp_data
|
||||
);
|
||||
|
||||
// Define interfaces
|
||||
ctrlport_if s_ctrlport_if(.clk(ctrlport_clk), .rst(ctrlport_rst));
|
||||
|
||||
// Map existing ports to ctrlport_if
|
||||
always_comb begin
|
||||
s_ctrlport_if.req.wr = s_ctrlport_req_wr;
|
||||
s_ctrlport_if.req.rd = s_ctrlport_req_rd;
|
||||
s_ctrlport_if.req.addr = s_ctrlport_req_addr;
|
||||
s_ctrlport_if.req.data = s_ctrlport_req_data;
|
||||
|
||||
s_ctrlport_resp_ack = s_ctrlport_if.resp.ack;
|
||||
s_ctrlport_resp_status = s_ctrlport_if.resp.status;
|
||||
s_ctrlport_resp_data = s_ctrlport_if.resp.data;
|
||||
end
|
||||
|
||||
// Instantiate ctrlport_if_clk_cross module
|
||||
ctrlport_if_terminator #(
|
||||
.BASE_ADDRESS(START_ADDRESS),
|
||||
.WINDOW_SIZE(LAST_ADDRESS - START_ADDRESS + 1)
|
||||
) terminator_inst (
|
||||
.s_ctrlport(s_ctrlport_if)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -1,50 +0,0 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_terminator.v
|
||||
// Description:
|
||||
// Returns an error for all ctrlport requests in given address range.
|
||||
|
||||
module ctrlport_terminator #(
|
||||
parameter START_ADDRESS = 0, // first address to generate response for
|
||||
parameter LAST_ADDRESS = 32 // last address (including) to generate response for
|
||||
)(
|
||||
//---------------------------------------------------------------
|
||||
// ControlPort slave
|
||||
//---------------------------------------------------------------
|
||||
input wire ctrlport_clk,
|
||||
input wire ctrlport_rst,
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
|
||||
output reg s_ctrlport_resp_ack,
|
||||
output wire [ 1:0] s_ctrlport_resp_status,
|
||||
output wire [31:0] s_ctrlport_resp_data
|
||||
);
|
||||
|
||||
`include "../core/ctrlport.vh"
|
||||
//vhook_nowarn s_ctrlport_req_addr
|
||||
//vhook_nowarn s_ctrlport_req_data
|
||||
|
||||
// drive acknowledgement on requests but not on reset
|
||||
always @(posedge ctrlport_clk) begin
|
||||
if (ctrlport_clk) begin
|
||||
if (ctrlport_rst) begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end else if ((s_ctrlport_req_addr >= START_ADDRESS) && (s_ctrlport_req_addr <= LAST_ADDRESS)) begin
|
||||
s_ctrlport_resp_ack <= s_ctrlport_req_wr | s_ctrlport_req_rd;
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// other outputs are fixed
|
||||
assign s_ctrlport_resp_status = CTRL_STS_CMDERR;
|
||||
assign s_ctrlport_resp_data = { CTRLPORT_DATA_W {1'b0}};
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,109 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_window
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// Copy requests from slave to master interface when s_ctrlport_req_addr is in
|
||||
// address range specified by BASE_ADDRESS and WINDOW_SIZE. The modules does
|
||||
// not use any registers and therefore does not need ctrlport_clk and
|
||||
// ctrlport_rst.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// BASE_ADDRESS: Base address of the memory window.
|
||||
// WINDOW_SIZE: Size of the memory window.
|
||||
//
|
||||
|
||||
module ctrlport_window
|
||||
import ctrlport_pkg::*;
|
||||
#(
|
||||
int BASE_ADDRESS = 0,
|
||||
int WINDOW_SIZE = 32
|
||||
) (
|
||||
// Slave Interface
|
||||
input logic s_ctrlport_req_wr,
|
||||
input logic s_ctrlport_req_rd,
|
||||
input logic [ CTRLPORT_ADDR_W-1:0] s_ctrlport_req_addr,
|
||||
input logic [ CTRLPORT_PORTID_W-1:0] s_ctrlport_req_portid,
|
||||
input logic [CTRLPORT_REM_EPID_W-1:0] s_ctrlport_req_rem_epid,
|
||||
input logic [ CTRLPORT_PORTID_W-1:0] s_ctrlport_req_rem_portid,
|
||||
input logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_req_data,
|
||||
input logic [ CTRLPORT_BYTE_EN_W-1:0] s_ctrlport_req_byte_en,
|
||||
input logic s_ctrlport_req_has_time,
|
||||
input logic [ CTRLPORT_TIME_W-1:0] s_ctrlport_req_time,
|
||||
output logic s_ctrlport_resp_ack,
|
||||
output logic [ CTRLPORT_STS_W-1:0] s_ctrlport_resp_status,
|
||||
output logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_resp_data,
|
||||
|
||||
// Master Interface
|
||||
output logic m_ctrlport_req_wr,
|
||||
output logic m_ctrlport_req_rd,
|
||||
output logic [ CTRLPORT_ADDR_W-1:0] m_ctrlport_req_addr,
|
||||
output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_portid,
|
||||
output logic [CTRLPORT_REM_EPID_W-1:0] m_ctrlport_req_rem_epid,
|
||||
output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_rem_portid,
|
||||
output logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_req_data,
|
||||
output logic [ CTRLPORT_BYTE_EN_W-1:0] m_ctrlport_req_byte_en,
|
||||
output logic m_ctrlport_req_has_time,
|
||||
output logic [ CTRLPORT_TIME_W-1:0] m_ctrlport_req_time,
|
||||
input logic m_ctrlport_resp_ack,
|
||||
input logic [ CTRLPORT_STS_W-1:0] m_ctrlport_resp_status,
|
||||
input logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_resp_data
|
||||
);
|
||||
|
||||
// Define interfaces
|
||||
logic dummy_clk = '0;
|
||||
logic dummy_rst = '0;
|
||||
ctrlport_if s_ctrlport_if(.clk(dummy_clk), .rst(dummy_rst));
|
||||
ctrlport_if m_ctrlport_if(.clk(dummy_clk), .rst(dummy_rst));;
|
||||
|
||||
// Map existing ports to ctrlport_if
|
||||
always_comb begin
|
||||
s_ctrlport_if.req.wr = s_ctrlport_req_wr;
|
||||
s_ctrlport_if.req.rd = s_ctrlport_req_rd;
|
||||
s_ctrlport_if.req.addr = s_ctrlport_req_addr;
|
||||
s_ctrlport_if.req.port_id = s_ctrlport_req_portid;
|
||||
s_ctrlport_if.req.remote_epid = s_ctrlport_req_rem_epid;
|
||||
s_ctrlport_if.req.remote_portid = s_ctrlport_req_rem_portid;
|
||||
s_ctrlport_if.req.data = s_ctrlport_req_data;
|
||||
s_ctrlport_if.req.byte_en = s_ctrlport_req_byte_en;
|
||||
s_ctrlport_if.req.has_time = s_ctrlport_req_has_time;
|
||||
s_ctrlport_if.req.timestamp = s_ctrlport_req_time;
|
||||
|
||||
s_ctrlport_resp_ack = s_ctrlport_if.resp.ack;
|
||||
s_ctrlport_resp_status = s_ctrlport_if.resp.status;
|
||||
s_ctrlport_resp_data = s_ctrlport_if.resp.data;
|
||||
end
|
||||
|
||||
// Instantiate ctrlport_if_clk_cross module
|
||||
ctrlport_if_window #(
|
||||
.BASE_ADDRESS(BASE_ADDRESS),
|
||||
.WINDOW_SIZE(WINDOW_SIZE)
|
||||
) window_inst (
|
||||
.s_ctrlport(s_ctrlport_if),
|
||||
.m_ctrlport(m_ctrlport_if)
|
||||
);
|
||||
|
||||
// Unpack ctrlport_if to output port
|
||||
always_comb begin
|
||||
m_ctrlport_req_wr = m_ctrlport_if.req.wr;
|
||||
m_ctrlport_req_rd = m_ctrlport_if.req.rd;
|
||||
m_ctrlport_req_addr = m_ctrlport_if.req.addr;
|
||||
m_ctrlport_req_portid = m_ctrlport_if.req.port_id;
|
||||
m_ctrlport_req_rem_epid = m_ctrlport_if.req.remote_epid;
|
||||
m_ctrlport_req_rem_portid = m_ctrlport_if.req.remote_portid;
|
||||
m_ctrlport_req_data = m_ctrlport_if.req.data;
|
||||
m_ctrlport_req_byte_en = m_ctrlport_if.req.byte_en;
|
||||
m_ctrlport_req_has_time = m_ctrlport_if.req.has_time;
|
||||
m_ctrlport_req_time = m_ctrlport_if.req.timestamp;
|
||||
|
||||
m_ctrlport_if.resp.ack = m_ctrlport_resp_ack;
|
||||
m_ctrlport_if.resp.status = ctrlport_status_t'(m_ctrlport_resp_status);
|
||||
m_ctrlport_if.resp.data = m_ctrlport_resp_data;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,73 +0,0 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_window
|
||||
//
|
||||
// Description:
|
||||
// Copy requests from slave to master interface when s_ctrlport_req_addr is in
|
||||
// address range specified by BASE_ADDRESS and WINDOW_SIZE. The modules does
|
||||
// not use any registers and therefore does not need ctrlport_clk and
|
||||
// ctrlport_rst.
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module ctrlport_window #(
|
||||
parameter BASE_ADDRESS = 0,
|
||||
parameter WINDOW_SIZE = 32
|
||||
) (
|
||||
// Slave Interface
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [ 9:0] s_ctrlport_req_portid,
|
||||
input wire [15:0] s_ctrlport_req_rem_epid,
|
||||
input wire [ 9:0] s_ctrlport_req_rem_portid,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
input wire [ 3:0] s_ctrlport_req_byte_en,
|
||||
input wire s_ctrlport_req_has_time,
|
||||
input wire [63:0] s_ctrlport_req_time,
|
||||
output wire s_ctrlport_resp_ack,
|
||||
output wire [ 1:0] s_ctrlport_resp_status,
|
||||
output wire [31:0] s_ctrlport_resp_data,
|
||||
|
||||
// Master Interface
|
||||
output wire m_ctrlport_req_wr,
|
||||
output wire m_ctrlport_req_rd,
|
||||
output wire [19:0] m_ctrlport_req_addr,
|
||||
output wire [ 9:0] m_ctrlport_req_portid,
|
||||
output wire [15:0] m_ctrlport_req_rem_epid,
|
||||
output wire [ 9:0] m_ctrlport_req_rem_portid,
|
||||
output wire [31:0] m_ctrlport_req_data,
|
||||
output wire [ 3:0] m_ctrlport_req_byte_en,
|
||||
output wire m_ctrlport_req_has_time,
|
||||
output wire [63:0] m_ctrlport_req_time,
|
||||
input wire m_ctrlport_resp_ack,
|
||||
input wire [ 1:0] m_ctrlport_resp_status,
|
||||
input wire [31:0] m_ctrlport_resp_data
|
||||
);
|
||||
|
||||
// Mask write and read flag
|
||||
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + WINDOW_SIZE);
|
||||
assign m_ctrlport_req_wr = s_ctrlport_req_wr & address_in_range;
|
||||
assign m_ctrlport_req_rd = s_ctrlport_req_rd & address_in_range;
|
||||
|
||||
// Forward all other signals untouched.
|
||||
assign m_ctrlport_req_addr = s_ctrlport_req_addr;
|
||||
assign m_ctrlport_req_portid = s_ctrlport_req_portid;
|
||||
assign m_ctrlport_req_rem_epid = s_ctrlport_req_rem_epid;
|
||||
assign m_ctrlport_req_rem_portid = s_ctrlport_req_rem_portid;
|
||||
assign m_ctrlport_req_data = s_ctrlport_req_data;
|
||||
assign m_ctrlport_req_byte_en = s_ctrlport_req_byte_en;
|
||||
assign m_ctrlport_req_has_time = s_ctrlport_req_has_time;
|
||||
assign m_ctrlport_req_time = s_ctrlport_req_time;
|
||||
|
||||
assign s_ctrlport_resp_ack = m_ctrlport_resp_ack;
|
||||
assign s_ctrlport_resp_status = m_ctrlport_resp_status;
|
||||
assign s_ctrlport_resp_data = m_ctrlport_resp_data;
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
Reference in New Issue
Block a user