fpga: lib: Add AXI4 (full) interface
Add a SystemVerilog interface for connecting AXI4 ports, and an associated header file with helper macros. Original-commit: 04d29e85b0c0698e3de96b54fd3f6e04eb439f74
This commit is contained in:
Andrew Moch
committed by
Aaron Rossetto
Aaron Rossetto
parent
d7acf31a38
commit
8cb9bdd331
@@ -0,0 +1,247 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Header File: AxiIf.vh
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// Description: Macros for use with AXI4(FULL)
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//
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//-----------------------------------------------------------------------------
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// AXI4 (FULL)
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//-----------------------------------------------------------------------------
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//
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// Difference between AXILITE and AXI(FULL)
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// Address channels contain
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// LEN, SIZE, BURST, LOCK, CACHE, PROT, QOS
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// Data Channels contain
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// LAST
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// Macro that drives o from i for all fields. Of course ready runs in the
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// counter direction.
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`define AXI4_ASSIGN(O,I) \
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/* write address channel */\
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``O.awaddr = ``I.awaddr;\
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``O.awlen = ``I.awlen;\
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``O.awsize = ``I.awsize;\
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``O.awburst = ``I.awburst;\
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``O.awlock = ``I.awlock;\
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``O.awcache = ``I.awcache;\
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``O.awprot = ``I.awprot;\
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``O.awqos = ``I.awqos;\
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``O.awvalid = ``I.awvalid;\
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``I.awready = ``O.awready;\
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/* write data channel */\
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``O.wdata = ``I.wdata;\
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``O.wstrb = ``I.wstrb;\
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``O.wlast = ``I.wlast;\
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``O.wvalid = ``I.wvalid;\
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``I.wready = ``O.wready;\
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/* write resp channel */\
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``I.bresp = ``O.bresp;\
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``I.bvalid = ``O.bvalid;\
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``O.bready = ``I.bready;\
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/* read address channel */\
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``O.araddr = ``I.araddr;\
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``O.arlen = ``I.arlen;\
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``O.arsize = ``I.arsize;\
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``O.arburst = ``I.arburst;\
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``O.arlock = ``I.arlock;\
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``O.arcache = ``I.arcache;\
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``O.arprot = ``I.arprot;\
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``O.arqos = ``I.arqos;\
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``O.arvalid = ``I.arvalid;\
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``I.arready = ``O.arready;\
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/* read resp channel */\
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``I.rdata = ``O.rdata;\
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``I.rresp = ``O.rresp;\
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``I.rlast = ``O.rlast;\
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``I.rvalid = ``O.rvalid;\
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``O.rready = ``I.rready;
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`define AXI4_PORT_ASSIGN(FORMAL,ACTUAL) \
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.``FORMAL``_aclk(``ACTUAL``.clk),\
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.``FORMAL``_sreset(``ACTUAL``.rst),\
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.``FORMAL``_araddr(``ACTUAL``.araddr),\
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.``FORMAL``_arlen(``ACTUAL``.arlen),\
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.``FORMAL``_arsize(``ACTUAL``.arsize),\
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.``FORMAL``_arburst(``ACTUAL``.arburst),\
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.``FORMAL``_arlock(``ACTUAL``.arlock),\
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.``FORMAL``_arcache(``ACTUAL``.arcache),\
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.``FORMAL``_arprot(``ACTUAL``.arprot),\
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.``FORMAL``_arqos(``ACTUAL``.arqos),\
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.``FORMAL``_arready(``ACTUAL``.arready),\
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.``FORMAL``_arvalid(``ACTUAL``.arvalid),\
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.``FORMAL``_awaddr(``ACTUAL``.awaddr),\
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.``FORMAL``_awlen(``ACTUAL``.awlen),\
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.``FORMAL``_awsize(``ACTUAL``.awsize),\
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.``FORMAL``_awburst(``ACTUAL``.awburst),\
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.``FORMAL``_awlock(``ACTUAL``.awlock),\
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.``FORMAL``_awcache(``ACTUAL``.awcache),\
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.``FORMAL``_awprot(``ACTUAL``.awprot),\
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.``FORMAL``_awqos(``ACTUAL``.awqos),\
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.``FORMAL``_awready(``ACTUAL``.awready),\
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.``FORMAL``_awvalid(``ACTUAL``.awvalid),\
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.``FORMAL``_bready(``ACTUAL``.bready),\
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.``FORMAL``_bresp(``ACTUAL``.bresp[1:0]),\
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.``FORMAL``_bvalid(``ACTUAL``.bvalid),\
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.``FORMAL``_rdata(``ACTUAL``.rdata),\
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.``FORMAL``_rready(``ACTUAL``.rready),\
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.``FORMAL``_rresp(``ACTUAL``.rresp[1:0]),\
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.``FORMAL``_rlast(``ACTUAL``.rlast),\
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.``FORMAL``_rvalid(``ACTUAL``.rvalid),\
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.``FORMAL``_wdata(``ACTUAL``.wdata),\
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.``FORMAL``_wready(``ACTUAL``.wready),\
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.``FORMAL``_wstrb(``ACTUAL``.wstrb),\
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.``FORMAL``_wlast(``ACTUAL``.wlast),\
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.``FORMAL``_wvalid(``ACTUAL``.wvalid),
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`define AXI4_PORT_ASSIGN_NR(FORMAL,ACTUAL) \
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.``FORMAL``_araddr(``ACTUAL``.araddr),\
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.``FORMAL``_arlen(``ACTUAL``.arlen),\
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.``FORMAL``_arsize(``ACTUAL``.arsize),\
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.``FORMAL``_arburst(``ACTUAL``.arburst),\
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.``FORMAL``_arlock(``ACTUAL``.arlock),\
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.``FORMAL``_arcache(``ACTUAL``.arcache),\
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.``FORMAL``_arprot(``ACTUAL``.arprot),\
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.``FORMAL``_arqos(``ACTUAL``.arqos),\
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.``FORMAL``_arready(``ACTUAL``.arready),\
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.``FORMAL``_arvalid(``ACTUAL``.arvalid),\
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.``FORMAL``_awaddr(``ACTUAL``.awaddr),\
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.``FORMAL``_awlen(``ACTUAL``.awlen),\
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.``FORMAL``_awsize(``ACTUAL``.awsize),\
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.``FORMAL``_awburst(``ACTUAL``.awburst),\
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.``FORMAL``_awlock(``ACTUAL``.awlock),\
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.``FORMAL``_awcache(``ACTUAL``.awcache),\
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.``FORMAL``_awprot(``ACTUAL``.awprot),\
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.``FORMAL``_awqos(``ACTUAL``.awqos),\
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.``FORMAL``_awready(``ACTUAL``.awready),\
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.``FORMAL``_awvalid(``ACTUAL``.awvalid),\
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.``FORMAL``_bready(``ACTUAL``.bready),\
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.``FORMAL``_bresp(``ACTUAL``.bresp[1:0]),\
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.``FORMAL``_bvalid(``ACTUAL``.bvalid),\
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.``FORMAL``_rdata(``ACTUAL``.rdata),\
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.``FORMAL``_rready(``ACTUAL``.rready),\
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.``FORMAL``_rresp(``ACTUAL``.rresp[1:0]),\
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.``FORMAL``_rlast(``ACTUAL``.rlast),\
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.``FORMAL``_rvalid(``ACTUAL``.rvalid),\
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.``FORMAL``_wdata(``ACTUAL``.wdata),\
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.``FORMAL``_wready(``ACTUAL``.wready),\
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.``FORMAL``_wstrb(``ACTUAL``.wstrb),\
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.``FORMAL``_wlast(``ACTUAL``.wlast),\
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.``FORMAL``_wvalid(``ACTUAL``.wvalid),
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`define AXI4_DEBUG_ASSIGN(O,I) \
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(* mark_debug = "true" *) logic [``I.ADDR_WIDTH-1:0] ``I``_debug_awaddr;\
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(* mark_debug = "true" *) logic [7:0] ``I``_debug_awlen;\
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(* mark_debug = "true" *) logic [2:0] ``I``_debug_awsize;\
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(* mark_debug = "true" *) logic [1:0] ``I``_debug_awburst;\
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(* mark_debug = "true" *) logic [0:0] ``I``_debug_awlock;\
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(* mark_debug = "true" *) logic [3:0] ``I``_debug_awcache;\
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(* mark_debug = "true" *) logic [2:0] ``I``_debug_awprot;\
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(* mark_debug = "true" *) logic [3:0] ``I``_debug_awqos;\
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(* mark_debug = "true" *) logic ``I``_debug_awvalid;\
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(* mark_debug = "true" *) logic ``I``_debug_awready;\
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(* mark_debug = "true" *) logic [``I.DATA_WIDTH-1:0] ``I``_debug_wdata;\
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(* mark_debug = "true" *) logic [``I.BYTES_PER_WORD-1:0] ``I``_debug_wstrb;\
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(* mark_debug = "true" *) logic ``I``_debug_wlast;\
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(* mark_debug = "true" *) logic ``I``_debug_wvalid;\
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(* mark_debug = "true" *) logic ``I``_debug_wready;\
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(* mark_debug = "true" *) logic [1:0] ``I``_debug_bresp;\
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(* mark_debug = "true" *) logic ``I``_debug_bvalid;\
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(* mark_debug = "true" *) logic ``I``_debug_bready;\
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(* mark_debug = "true" *) logic [``I.ADDR_WIDTH-1:0] ``I``_debug_araddr;\
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(* mark_debug = "true" *) logic [7:0] ``I``_debug_arlen;\
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(* mark_debug = "true" *) logic [2:0] ``I``_debug_arsize;\
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(* mark_debug = "true" *) logic [1:0] ``I``_debug_arburst;\
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(* mark_debug = "true" *) logic [0:0] ``I``_debug_arlock;\
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(* mark_debug = "true" *) logic [3:0] ``I``_debug_arcache;\
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(* mark_debug = "true" *) logic [2:0] ``I``_debug_arprot;\
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(* mark_debug = "true" *) logic [3:0] ``I``_debug_arqos;\
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(* mark_debug = "true" *) logic ``I``_debug_arvalid;\
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(* mark_debug = "true" *) logic ``I``_debug_arready;\
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(* mark_debug = "true" *) logic [``I.DATA_WIDTH-1:0] ``I``_debug_rdata;\
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(* mark_debug = "true" *) logic [1:0] ``I``_debug_rresp;\
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(* mark_debug = "true" *) logic ``I``_debug_rlast;\
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(* mark_debug = "true" *) logic ``I``_debug_rvalid;\
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(* mark_debug = "true" *) logic ``I``_debug_rready;\
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always_comb begin\
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/* write address channel */\
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``I``_debug_awaddr = ``I.awaddr;\
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``I``_debug_awlen = ``I.awlen;\
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``I``_debug_awsize = ``I.awsize;\
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``I``_debug_awburst = ``I.awburst;\
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``I``_debug_awlock = ``I.awlock;\
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``I``_debug_awcache = ``I.awcache;\
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``I``_debug_awprot = ``I.awprot;\
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``I``_debug_awqos = ``I.awqos;\
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``I``_debug_awvalid = ``I.awvalid;\
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``I.awready = ``I``_debug_awready;\
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/* write data channel */\
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``I``_debug_wdata = ``I.wdata;\
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``I``_debug_wstrb = ``I.wstrb;\
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``I``_debug_wlast = ``I.wlast;\
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``I``_debug_wvalid = ``I.wvalid;\
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``I.wready = ``I``_debug_wready;\
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/* write resp channel */\
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``I.bresp = ``I``_debug_bresp;\
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``I.bvalid = ``I``_debug_bvalid;\
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``I``_debug_bready = ``I.bready;\
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/* read address channel */\
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``I``_debug_araddr = ``I.araddr;\
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``I``_debug_arlen = ``I.arlen;\
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``I``_debug_arsize = ``I.arsize;\
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``I``_debug_arburst = ``I.arburst;\
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``I``_debug_arlock = ``I.arlock;\
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``I``_debug_arcache = ``I.arcache;\
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``I``_debug_arprot = ``I.arprot;\
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``I``_debug_arqos = ``I.arqos;\
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``I``_debug_arvalid = ``I.arvalid;\
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``I.arready = ``I``_debug_arready;\
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/* read resp channel */\
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``I.rdata = ``I``_debug_rdata;\
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``I.rresp = ``I``_debug_rresp;\
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``I.rlast = ``I``_debug_rlast;\
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``I.rvalid = ``I``_debug_rvalid;\
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``I``_debug_rready = ``I.rready;\
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end\
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always_comb begin\
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/* write address channel */\
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``O.awaddr = ``I``_debug_awaddr;\
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``O.awlen = ``I``_debug_awlen;\
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``O.awsize = ``I``_debug_awsize;\
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``O.awburst = ``I``_debug_awburst;\
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``O.awlock = ``I``_debug_awlock;\
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``O.awcache = ``I``_debug_awcache;\
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``O.awprot = ``I``_debug_awprot;\
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``O.awqos = ``I``_debug_awqos;\
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``O.awvalid = ``I``_debug_awvalid;\
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``I``_debug_awready = ``O.awready;\
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/* write data channel */\
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``O.wdata = ``I``_debug_wdata;\
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``O.wstrb = ``I``_debug_wstrb;\
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``O.wlast = ``I``_debug_wlast;\
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``O.wvalid = ``I``_debug_wvalid;\
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``I``_debug_wready = ``O.wready;\
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/* write resp channel */\
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``I``_debug_bresp = ``O.bresp;\
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``I``_debug_bvalid = ``O.bvalid;\
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``O.bready = ``I``_debug_bready;\
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/* read address channel */\
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``O.araddr = ``I``_debug_araddr;\
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``O.arlen = ``I``_debug_arlen;\
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``O.arsize = ``I``_debug_arsize;\
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``O.arburst = ``I``_debug_arburst;\
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``O.arlock = ``I``_debug_arlock;\
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``O.arcache = ``I``_debug_arcache;\
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``O.arprot = ``I``_debug_arprot;\
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``O.arqos = ``I``_debug_arqos;\
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``O.arvalid = ``I``_debug_arvalid;\
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``I``_debug_arready = ``O.arready;\
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/* read resp channel */\
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``I``_debug_rdata = ``O.rdata;\
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``I``_debug_rresp = ``O.rresp;\
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``I``_debug_rvlast = ``O.rlast;\
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``I``_debug_rvalid = ``O.rvalid;\
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``O.rready = ``I``_debug_rready;\
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end
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