fpga: lib: Add AXI4 (full) interface

Add a SystemVerilog interface for connecting AXI4 ports, and an associated header file with helper macros. Original-commit: 04d29e85b0c0698e3de96b54fd3f6e04eb439f74
2021-06-03 11:26:54 -05:00
parent d7acf31a38
commit 8cb9bdd331
4 changed files with 619 additions and 0 deletions
@@ -0,0 +1,13 @@
+#
+# Copyright 2021 Ettus Research, A National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# RFNoC Utility Sources
+##################################################
+AXI4_SV_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/axi4_sv/, \
+PkgAxi.sv \
+AxiIf.sv \
+))